Patents by Inventor Takamasa Tanaka
Takamasa Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935998Abstract: A battery device comprises a nonaqueous electrolyte secondary battery provided with an electric power generating element and a pressing member which presses the electric power generating element in the stacking direction. The electric power generating element comprises: a positive electrode with a positive electrode active material layer of a positive electrode active material on the surface of a positive electrode collector; a negative electrode with a negative electrode active material layer of a negative electrode active material on the surface of a negative electrode collector; and a separator which holds an electrolyte solution. This battery device satisfies (1) 0.1<(T1?T2)/T1×100<5, where T1 is the thickness of the thickest portion of the electric power generating element in the stacking direction, and T2 is the thickness of the thinnest portion of the of the electric power generating element in the stacking direction.Type: GrantFiled: May 22, 2019Date of Patent: March 19, 2024Assignee: Nissan Motor Co., Ltd.Inventors: Takamasa Nakagawa, Takeshi Nakano, Hiroyuki Tanaka, Yusuke Nakashima, Naofumi Shoji
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Publication number: 20200180022Abstract: An aluminum particle group composed of aluminum particles, as observed in an image thereof obtained through a scanning electron microscope, has an average circularity of 0.75 or more, and an average particle diameter of D50 of 10 ?m or more and less than 100 ?m, and satisfies A×3?B and also satisfying D<C where A represents the number of aluminum particles having a diameter of less than 5 ?m, B represents the number of aluminum particles having a diameter of 10 ?m or more, C represents the number of aluminum particles with no satellite, and D represents the number of aluminum particles having satellites.Type: ApplicationFiled: October 24, 2016Publication date: June 11, 2020Applicant: TOYO ALUMINIUM KABUSHIKI KAISHAInventors: Isao MURAKAMI, Jun KUSUI, Takamasa TANAKA, Kenta ISHIGAMI
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Publication number: 20200140276Abstract: To provide an aluminum nitride-based powder that includes less amount of fine powder that is hard to be completely removed, has superior filling performance for a polymeric material, and also has thermal conductivity. The present invention relates to an aluminum nitride-based powder comprising aluminum nitride-based particles, wherein (1) the average particle size D50 is 15 to 200 ?m; (2) a content of particles having a particle size of at most 5 ?m is at most 60% on a particle number basis; (3) a content of an alkaline earth metal element and a rare-earth element is at most 0.1 weight %; (4) a content of oxygen is at most 0.5 weight %; and (5) a content of silicon is at most 1000 ppm by weight, and a content of iron is at most 1000 ppm by weight.Type: ApplicationFiled: May 17, 2018Publication date: May 7, 2020Inventors: Takamasa Tanaka, Jun Kusui, Katsumi Nakashima, Kazuya Higashimura, Shuhei Kanno
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Patent number: 9935232Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.Type: GrantFiled: November 4, 2015Date of Patent: April 3, 2018Assignee: Toshiba Memory CorporationInventors: Gen Toyota, Shouta Inoue, Susumu Yamamoto, Takamasa Tanaka, Takamitsu Yoshida, Kazumasa Tanida
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Publication number: 20160268469Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.Type: ApplicationFiled: November 4, 2015Publication date: September 15, 2016Inventors: Gen Toyota, Shouta Inoue, Susumu Yamamoto, Takamasa Tanaka, Takamitsu Yoshida, Kazumasa Tanida
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Patent number: 8193740Abstract: A control circuit for a discharge lamp, which can improve the lighting performance of the discharge lamp while realizing low power consumption, and a light source device are provided. The resistance value of the variable resistor (RC1, RC2) is not switched to the low resistance (R02) for steady discharge at the fourth time t4, but is switched to the low resistance (R02) at the fifth time t5, after lowering of power supply to the filament. With such control, a change in the lamp impedance is absorbed sufficiently by the variable resistor while power supply to the filament is being lowered and, therefore, destabilization of discharge is reduced and the lighting performance is improved.Type: GrantFiled: May 1, 2008Date of Patent: June 5, 2012Assignee: Hamamatsu Photonics K.K.Inventors: Kazuo Ueno, Yoshinobu Ito, Takamasa Tanaka, Koji Matsushita
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Publication number: 20100194309Abstract: A control circuit for a discharge lamp, which can improve the lighting performance of the discharge lamp while realizing low power consumption, and a light source device are provided. The resistance value of the variable resistor (RC1, RC2) is not switched to the low resistance (R02) for steady discharge at the fourth time t4, but is switched to the low resistance (R02) at the fifth time t5, after lowering of power supply to the filament. With such control, a change in the lamp impedance is absorbed sufficiently by the variable resistor while power supply to the filament is being lowered and, therefore, destabilization of discharge is reduced and the lighting performance is improved.Type: ApplicationFiled: May 1, 2008Publication date: August 5, 2010Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Kazuo Ueno, Yoshinobu Ito, Takamasa Tanaka, Koji Matsushita
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Patent number: 6831002Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: GrantFiled: September 13, 2002Date of Patent: December 14, 2004Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Publication number: 20030134509Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: ApplicationFiled: September 13, 2002Publication date: July 17, 2003Inventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Patent number: 5841217Abstract: In a surface mounting crystal unit comprising a quartz plate, a receptacle-like terminal member holding the quartz plate therein in such a way as to enable it to oscillate, and a lid covering an opening of the terminal member, the quartz plate is prepared in the shape of a rectangular parallelepiped and disposed such that one or both of shorter sides of the quartz plate at its both ends can be fixedly attached to flat surface portions of the terminal member with an electrically conductive adhesive of high plasticity so that the impact of a drop is buffered by the adhesive. A likelihood of any leakage is minimized by airtight bonding of the lid to the opening of the terminal member with an inorganic material such as a solder, and the like. Furthermore, crystal impedance is lowered by producing a vacuum inside the terminal member airtightly bonded by the lid.Type: GrantFiled: March 12, 1997Date of Patent: November 24, 1998Assignee: Citizen Watch Co., Ltd.Inventors: Shigeru Kizaki, Yoshikazu Sakaguchi, Hachiro Kimura, Kazuo Murata, Issei Nakayama, Takamasa Tanaka, Toshihide Ohi