Abstract: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.

Abstract: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.

Abstract: A method of manufacturing a semiconductor device includes performing a first etching process on a gate electrode layer to form a gate electrode of a first transistor group including a transistor pair, and performing a second etching process different from the first etching on the gate electrode layer to form a gate electrode of a second transistor group. Forming in this way enables characteristics of the transistor pair to be the same.

Abstract: A semiconductor device includes an interlayer formed to cover a semiconductor substrate, a circuit element, a preventing diffusion region, a power supply line and a ground line. The power supply line is formed on the interlayer to supply a positive voltage to the circuit element. The ground line is formed on the interlayer on an opposite side to the circuit element with respective to the power supply line. The circuit element is formed in a surface portion of a semiconductor substrate. The preventing diffusion region is formed in a surface portion of the semiconductor substrate in correspondence to the power supply line, and is applied with a predetermined positive voltage.