Abstract: An object of the present disclosure is to provide a semiconductor device capable of confirming withstand voltage of a snubber circuit after providing the snubber circuit and a method of manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: an insulating substrate; a circuit patterns provided on the insulating substrate; a snubber circuit substrate provided on the insulating substrate separately from the circuit patterns; a resistance provided on one of the circuit patterns and the snubber circuit substrate; a capacitor provided on another one of the circuit patterns and the snubber circuit substrate; and at least one semiconductor element electrically connected to the resistance and the capacitor.

Abstract: An object of the present disclosure is to provide a semiconductor device capable of confirming withstand voltage of a snubber circuit after providing the snubber circuit and a method of manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: an insulating substrate; a circuit patterns provided on the insulating substrate; a snubber circuit substrate provided on the insulating substrate separately from the circuit patterns; a resistance provided on one of the circuit patterns and the snubber circuit substrate; a capacitor provided on another one of the circuit patterns and the snubber circuit substrate; and at least one semiconductor element electrically connected to the resistance and the capacitor.

Abstract: A semiconductor module includes an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer, a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member, and a heat sink that is fixed to the second metal pattern with a second metal joining member, wherein the semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm, and the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive.

Abstract: A semiconductor device according to the present invention includes a resist provided so as to have an opening on a metal pattern, the resist having a protrusion part protruding into the opening, and the semiconductor device further includes a semiconductor element having an outside dimension smaller than an outside dimension of the opening excluding the protrusion, and solder provided inside the opening to join the metal pattern and the semiconductor element, wherein the protrusion part of the resist includes a plurality of protrusions that overlap with the semiconductor element in a plan view and regulate a thickness direction of the semiconductor element.

Abstract: A semiconductor device according to the present invention includes a resist provided so as to have an opening on a metal pattern, the resist having a protrusion part protruding into the opening, and the semiconductor device further includes a semiconductor element having an outside dimension smaller than an outside dimension of the opening excluding the protrusion, and solder provided inside the opening to join the metal pattern and the semiconductor element, wherein the protrusion part of the resist includes a plurality of protrusions that overlap with the semiconductor element in a plan view and regulate a thickness direction of the semiconductor element.

Abstract: A semiconductor module includes an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer, a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member, and a heat sink that is fixed to the second metal pattern with a second metal joining member, wherein the semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm, and the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: An electronic component mounting device includes an insulating substrate having a metal pattern formed thereon and a MELF electronic component. The MELF electronic component is fitted into a first receiving portion configured with the metal pattern and the insulating substrate exposed from a lacking portion of the metal pattern. The electronic component mounting device further includes a conductive member formed between the MELF electronic component and the metal pattern, and the conductive member is not formed between the MELF electronic component and the insulating substrate.

Abstract: A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet.

Abstract: A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

Abstract: A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet.

Abstract: A power module includes: a base plate having a front surface provided with positioning wire bonding portions; an insulating substrate provided with hole portions accommodating the positioning wire bonding portions on a side of a back surface facing the base plate, and fixed to the base plate with being positioned with respect to the base plate by the hole portions accommodating the positioning wire bonding portions; and a semiconductor chip arranged on a side of a front surface of the insulating substrate opposite to the back surface.

Abstract: A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: An electronic component mounting device includes an insulating substrate having a metal pattern formed thereon and a MELF electronic component. The MELF electronic component is fitted into a first receiving portion configured with the metal pattern and the insulating substrate exposed from a lacking portion of the metal pattern. The electronic component mounting device further includes a conductive member formed between the MELF electronic component and the metal pattern, and the conductive member is not formed between the MELF electronic component and the insulating substrate.

Abstract: A power module includes: a base plate having a front surface provided with positioning wire bonding portions; an insulating substrate provided with hole portions accommodating the positioning wire bonding portions on a side of a back surface facing the base plate, and fixed to the base plate with being positioned with respect to the base plate by the hole portions accommodating the positioning wire bonding portions; and a semiconductor chip arranged on a side of a front surface of the insulating substrate opposite to the back surface.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.