Patents by Inventor Takamichi Miyamoto
Takamichi Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230368580Abstract: A liveness detection apparatus (2000) causes a display apparatus (20) to display a plurality of screens (30). At least one of the plurality of screens (30) has a plurality of regions (32). At least two of the plurality of regions (32) include different indications. The liveness detection apparatus (2000) acquires a plurality of captured images (40). The captured image (40) is generated by capturing an image of a target object (50) with a camera (10) while the screen (30) is displayed. The liveness detection apparatus (2000) determines whether or not the target object (50) is a living body by using the plurality of captured images (40).Type: ApplicationFiled: April 16, 2021Publication date: November 16, 2023Applicant: NEC CorporationInventors: Takamichi MIYAMOTO, Koichi TAKAHASHI
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Publication number: 20230368581Abstract: A liveness detection apparatus (2000) causes a display apparatus (20) to display a plurality of screens (30). At least one of the plurality of screens (30) has a plurality of regions (32). At least two of the plurality of regions (32) include different indications. The liveness detection apparatus (2000) acquires a plurality of captured images (40). The captured image (40) is generated by capturing an image of a target object (50) with a camera (10) while the screen (30) is displayed. The liveness detection apparatus (2000) determines whether or not the target object (50) is a living body by using the plurality of captured images (40).Type: ApplicationFiled: October 9, 2020Publication date: November 16, 2023Applicant: NEC CorporationInventors: Koichi TAKAHASHI, Takamichi MIYAMOTO
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Publication number: 20220406094Abstract: An authentication apparatus (2) includes: an iris authentication unit (217) for authenticating an authentication target based on iris feature information related to feature of an iris of the authentication target in a captured image (100) obtained by capturing an image of the authentication target (TP); and an image determination unit (214) for determining, based on face feature information related to feature of a face of the authentication target in the captured image, whether or not the captured image satisfies a predetermined condition that should be satisfied as an image used to authenticate the authentication target by using the iris feature information, an operation of the iris authentication unit in a case where it is determined that the captured image satisfies the predetermined condition is different from an operation of the iris authentication unit in a case where it is determined that the captured image does not satisfy the predetermined condition.Type: ApplicationFiled: October 30, 2019Publication date: December 22, 2022Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Publication number: 20220383658Abstract: An imaging apparatus for authentication includes: a first imaging unit that obtains a first image used in a first authentication process by imaging a target person; a second imaging unit that obtains a second image used in a second image process by imaging the target person in an imaging range narrower than that of the first imaging unit; a drive unit that integrally drives the first imaging unit and the second imaging unit; and a drive control unit that controls the drive unit on the basis of the first image.Type: ApplicationFiled: November 5, 2019Publication date: December 1, 2022Applicants: NEC Corporation, NEC Platforms, Ltd.Inventors: Toshinobu OGATSU, Ryoma OAMI, Toshiyuki SASHIHARA, Takamichi MIYAMOTO, Ryuichi AKASHI, Ryo YAMAKABE, Daisuke SHIMADA
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Publication number: 20220188382Abstract: An information processing apparatus 1 includes: a cost calculation unit 2 configured to calculate, using input data information indicating a data size of input data, kernel information indicating a data size of a kernel, and parameter information indicating a parameter to be used in convolution processing, for each matrix processing operation to be executed in the convolution processing, a cost of the matrix processing based on memory access; and a matrix processing selection unit 3 configured to make combinations of the matrix processing operations, add up the costs corresponding to the respective matrix processing operations included in each combination, and selects a combination of the matrix processing corresponding to the added-up cost that is smallest among costs added up for the respective combinations.Type: ApplicationFiled: February 28, 2022Publication date: June 16, 2022Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Publication number: 20220179924Abstract: An information processing apparatus 1 includes: a cost calculation unit 2 configured to calculate, using input data information indicating a data size of input data, kernel information indicating a data size of a kernel, and parameter information indicating a parameter to be used in convolution processing, for each matrix processing operation to be executed in the convolution processing, a cost of the matrix processing based on memory access; and a matrix processing selection unit 3 configured to make combinations of the matrix processing operations, add up the costs corresponding to the respective matrix processing operations included in each combination, and selects a combination of the matrix processing corresponding to the added-up cost that is smallest among costs added up for the respective combinations.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Publication number: 20220179923Abstract: An information processing apparatus 1 includes: a cost calculation unit 2 configured to calculate, using input data information indicating a data size of input data, kernel information indicating a data size of a kernel, and parameter information indicating a parameter to be used in convolution processing, for each matrix processing operation to be executed in the convolution processing, a cost of the matrix processing based on memory access; and a matrix processing selection unit 3 configured to make combinations of the matrix processing operations, add up the costs corresponding to the respective matrix processing operations included in each combination, and selects a combination of the matrix processing corresponding to the added-up cost that is smallest among costs added up for the respective combinations.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Publication number: 20210312013Abstract: An information processing apparatus 1 includes: a cost calculation unit 2 configured to calculate, using input data information indicating a data size of input data, kernel information indicating a data size of a kernel, and parameter information indicating a parameter to be used in convolution processing, for each matrix processing operation to be executed in the convolution processing, a cost of the matrix processing based on memory access; and a matrix processing selection unit 3 configured to make combinations of the matrix processing operations, add up the costs corresponding to the respective matrix processing operations included in each combination, and selects a combination of the matrix processing corresponding to the added-up cost that is smallest among costs added up for the respective combinations.Type: ApplicationFiled: August 7, 2018Publication date: October 7, 2021Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Patent number: 10878263Abstract: This collation processing device 20 speeds up collation processing when characteristics indicated by characteristic points in a collation source and a collation destination are classified into any of characteristic types, by including: an acquisition unit 21 acquiring a weighting value 210 of collation indicating the degree of collation for each combination of characteristic types of the collation source and collation destination; a classification unit 22 classifying the characteristic points into groups, based on the weighting value 210; a representative value determination unit 23 determining, for each group, a representative value of the weighting value 210; a rough collation unit 24 performing collation per group, using the representative value; a determination unit 25 determining whether the collation result satisfies a determination criterion; and a fine collation unit 26 performing collation by using the weighting value 210, only when the determination criterion is satisfied.Type: GrantFiled: December 13, 2017Date of Patent: December 29, 2020Assignee: NEC CORPORATIONInventor: Takamichi Miyamoto
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Patent number: 10824407Abstract: A program conversion device includes converting a program including second loop processing that repeats first processing and determination processing a plurality of times to a program including third loop processing and fourth loop processing; converting the converted program to a first-number-of-times repeating processing that includes second-number-of-times repeating processing of the first loop processing and the second-number-of-times repeating processing of the determination processing; converting the first processing and the determination processing to processing that accesses to memory areas that are different for fourth loop processing and that are continuous in a processing order in the fourth loop processing; and exchanging a processing order of the fourth loop processing and the first loop processing, wherein the third loop processing is the-first-number-of-times repeating processing related to the second loop processing, and the fourth loop processing is the-second-number-of-times repeating procesType: GrantFiled: December 28, 2016Date of Patent: November 3, 2020Assignee: NEC CORPORATIONInventor: Takamichi Miyamoto
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Patent number: 10789203Abstract: A process set selection unit generates, based on a process set comprising a processing block performing arithmetic on a group of inputs and a group of outputs produced by the processing block, a group of new inputs having a combination number less than that of the group of inputs and a new processing block for the group of new inputs. A reuse execution unit prepares, based on the new processing block for performing arithmetic on the group of new inputs and a group of outputs produced by the new processing block, an associated result which associates the group of new inputs with the group of outputs, produces the group of outputs obtained from the association result if the group of new inputs have values equal to those of the group of inputs, and, if not, executes the new processing blocks to register an executed result to the associated result.Type: GrantFiled: May 22, 2017Date of Patent: September 29, 2020Assignee: NEC CORPORATIONInventor: Takamichi Miyamoto
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Publication number: 20200264855Abstract: A program conversion device includes converting a program including second loop processing that repeats first processing and determination processing a plurality of times to a program including third loop processing and fourth loop processing; converting the converted program to a first-number-of-times repeating processing that includes second-number-of-times repeating processing of the first loop processing and the second-number-of-times repeating processing of the determination processing; converting the first processing and the determination processing to processing that accesses to memory areas that are different for fourth loop processing and that are continuous in a processing order in the fourth loop processing; and exchanging a processing order of the fourth loop processing and the first loop processing, wherein the third loop processing is the-first-number-of-times repeating processing related to the second loop processing, and the fourth loop processing is the-second-number-of-times repeating procesType: ApplicationFiled: December 28, 2016Publication date: August 20, 2020Applicant: NEC CORPORATIONInventor: Takamichi MIYAMOTO
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Publication number: 20200074203Abstract: This collation processing device 20 speeds up collation processing when characteristics indicated by characteristic points in a collation source and a collation destination are classified into any of characteristic types, by including: an acquisition unit 21 acquiring a weighting value 210 of collation indicating the degree of collation for each combination of characteristic types of the collation source and collation destination; a classification unit 22 classifying the characteristic points into groups, based on the weighting value 210; a representative value determination unit 23 determining, for each group, a representative value of the weighting value 210; a rough collation unit 24 performing collation per group, using the representative value; a determination unit 25 determining whether the collation result satisfies a determination criterion; and a fine collation unit 26 performing collation by using the weighting value 210, only when the determination criterion is satisfied.Type: ApplicationFiled: December 13, 2017Publication date: March 5, 2020Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Publication number: 20190138495Abstract: A process set selection unit generates, based on a process set comprising a processing block performing arithmetic on a group of inputs and a group of outputs produced by the processing block, a group of new inputs having a combination number less than that of the group of inputs and a new processing block for the group of new inputs. A reuse execution unit prepares, based on the new processing block for performing arithmetic on the group of new inputs and a group of outputs produced by the new processing block, an associated result which associates the group of new inputs with the group of outputs, produces the group of outputs obtained from the association result if the group of new inputs have values equal to those of the group of inputs, and, if not, executes the new processing blocks to register an executed result to the associated result.Type: ApplicationFiled: May 22, 2017Publication date: May 9, 2019Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Patent number: 10120602Abstract: A data placement destination determination device enables efficiency improvement of the execution time of a program that is executed in a system mounted with a plurality of memories having differing memory bandwidth. This device includes: a program information acquisition unit acquiring required bandwidth and memory size; a system information acquisition unit acquiring the memory bandwidth and size of a candidate memory at a placement destination; a priority setting unit setting priority based on required bandwidth and priority; a first placement destination determination unit determining a placement destination for the data of the program concerned within a range that does not exceed memory size and bandwidth based on the set priorities; and a second placement destination determination unit determining a placement destination within a range that does not exceed memory size based on the set priorities, the required bandwidth of the program concerned, and the memory bandwidth of the candidate memory.Type: GrantFiled: March 22, 2016Date of Patent: November 6, 2018Assignee: NEC CORPORATIONInventor: Takamichi Miyamoto
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Patent number: 9940053Abstract: The present invention discloses an information-processing device with which it is possible to improve throughput by avoiding application stoppage due to the shortage of a memory area, and by reducing the application processing time needed for reserving and freeing memory.Type: GrantFiled: May 26, 2015Date of Patent: April 10, 2018Assignee: NEC CORPORATIONInventor: Takamichi Miyamoto
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Publication number: 20180081581Abstract: A data placement destination determination device enables efficiency improvement of the execution time of a program that is executed in a system mounted with a plurality of memories having differing memory bandwidth. This device includes: a program information acquisition unit acquiring required bandwidth and memory size; a system information acquisition unit acquiring the memory bandwidth and size of a candidate memory at a placement destination; a priority setting unit setting priority based on required bandwidth and priority; a first placement destination determination unit determining a placement destination for the data of the program concerned within a range that does not exceed memory size and bandwidth based on the set priorities; and a second placement destination determination unit determining a placement destination within a range that does not exceed memory size based on the set priorities, the required bandwidth of the program concerned, and the memory bandwidth of the candidate memory.Type: ApplicationFiled: March 22, 2016Publication date: March 22, 2018Inventor: Takamichi MIYAMOTO
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Publication number: 20170199816Abstract: A pattern matching process between data sets each including a plurality of types of data elements is executed at high speed. A data storage device (200) places a predetermined number of data sets on a memory of a computer. The data set includes a plurality of types of data elements. In the computer, a program for repeatedly carrying out a set of processes for the predetermined number of the data sets is executed. The set of processes includes carrying out a predetermined operation sequentially for respective types of data elements in the data set when a predetermined condition is satisfied.Type: ApplicationFiled: June 17, 2015Publication date: July 13, 2017Applicant: NEC CorporationInventor: Takamichi Miyamoto
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Publication number: 20170083258Abstract: The present invention discloses an information-processing device with which it is possible to improve throughput by avoiding application stoppage due to the shortage of a memory area, and by reducing the application processing time needed for reserving and freeing memory.Type: ApplicationFiled: May 26, 2015Publication date: March 23, 2017Applicant: NEC CorporationInventor: Takamichi MIYAMOTO
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Patent number: 9483324Abstract: Provided is to a program conversion device which can use processor resources of a system to the utmost and enhance performance ability. The program conversion device includes: specific process determining unit which determines a range of a partial program to perform a specific process in a target program which includes a first execution scheme specifying program which can be executed in parallel with a first ratio of being a usage ratio of a first usage quantity with respect to a first resource of a first processor and a second usage quantity with respect to a second resource of a second processor; and process converting unit which converts the partial program into a second execution scheme specifying program which can be executed in parallel with a second ratio of being the usage ratio different from the first ratio.Type: GrantFiled: June 12, 2013Date of Patent: November 1, 2016Assignee: NEC CORPORATIONInventor: Takamichi Miyamoto