Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including: a plurality of memory cells stacked above a substrate, and a plurality of word lines respectively coupled to gates of the plurality of memory cells and extending in a first direction; and a first film including a first area above the memory cell array and a second area different from the first area, and having a compressive stress higher than silicon oxide. In the first area, a plurality of first trenches extending in the first direction are aligned in a second direction that intersects the first direction. In the second area, a second trench in a mesh form is provided.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including: a plurality of memory cells stacked above a substrate, and a plurality of word lines respectively coupled to gates of the plurality of memory cells and extending in a first direction; and a first film including a first area above the memory cell array and a second area different from the first area, and having a compressive stress higher than silicon oxide. In the first area, a plurality of first trenches extending in the first direction are aligned in a second direction that intersects the first direction. In the second area, a second trench in a mesh form is provided.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming a first insulating film and a wiring pattern and forming a second insulating film on the upper side of these. Further, a process of making holes in the second insulating film simultaneously at position where the wiring pattern is placed and position where the wiring pattern is not formed is performed. Thus, a first hole extending down to the wiring pattern and a second hole extending down to the first insulating film are formed. Then part of the first insulating film is removed through the second hole, and forming an air gap between a first portion and a second portion of the wiring pattern.

Abstract: A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.

Abstract: A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x?890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5?x?22.1).

Abstract: A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.

Abstract: A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x?890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5?x?22.1).

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

Abstract: Disclosed is a semiconductor device comprising an insulating film, a capacitor formed on the insulating film and comprising a bottom electrode, a top electrode, and a dielectric film between the top electrode and the bottom electrode, a plug passing through the insulating film and connected to the bottom electrode, and an oxygen barrier film covering the capacitor and the insulating film, and having lower oxygen permeability than the insulating film.

Abstract: A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.