Patents by Inventor Takamitsu Harada

Takamitsu Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698420
    Abstract: The present invention relates to Li-Ni composite oxide particles that exhibit a high initial discharge capacity and are excellent in thermal stability when used as a positive electrode active substance for non-aqueous electrolyte secondary batteries, and a process for producing the Li-Nicomposite oxide particles. The Li-Ni composite oxide particles of the present invention have a composition of LixNi1?y?a?bCoyM1aM2bO2 wherein x, y, a and b represent 1.00?x?1.10; 0<y?0.25; 0<a?0.25; and 0?b?0.10, respectively; M1 is at least one element selected from the group consisting of Al and Mn; and M2 is at least one element selected from the group consisting of Zr and Mg, in which a product of a metal occupancy (%) of lithium sites of the Li-Ni composite oxide as determined by Rietveld analysis of X-ray diffraction thereof and a crystallite size (nm) of the Li-Ni composite oxide as determined by the Rietveld analysis is not less than 700 and not more than 1400.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 4, 2017
    Assignee: TODA KOGYO CORP.
    Inventors: Kazutoshi Ishizaki, Kazuhiko Kikuya, Takahiko Sugihara, Teruaki Santoki, Takamitsu Harada, Masaki Nishimura, Yuji Mishima, Hideaki Sadamura
  • Publication number: 20150249248
    Abstract: The present invention relates to Li—Ni composite oxide particles that exhibit a high initial discharge capacity and are excellent in thermal stability when used as a positive electrode active substance for non-aqueous electrolyte secondary batteries, and a process for producing the Li—Ni composite oxide particles. The Li—Ni composite oxide particles of the present invention have a composition of LixNi1-y-a-bCoyM1aM2bO2 wherein x, y, a and b represent 1.00?x?1.10; 0<y?0.25; 0<a?0.25; and 0?b?0.10, respectively; M1 is at least one element selected from the group consisting of Al and Mn; and M2 is at least one element selected from the group consisting of Zr and Mg, in which a product of a metal occupancy (%) of lithium sites of the Li—Ni composite oxide as determined by Rietveld analysis of X-ray diffraction thereof and a crystallite size (nm) of the Li—Ni composite oxide as determined by the Rietveld analysis is not less than 700 and not more than 1400.
    Type: Application
    Filed: October 15, 2013
    Publication date: September 3, 2015
    Inventors: Kazutoshi Ishizaki, Kazuhiko Kikuya, Takahiko Sugihara, Teruaki Santoki, Takamitsu Harada, Masaki Nishimura, Yuji Mishima, Hideaki Sadamura
  • Publication number: 20050089723
    Abstract: There is provided a magnetic recording medium which is well evaluated in a running reliability, has small amount of seizing on a magnetic head, suppresses a wear rate of the magnetic head, and maintains high reproduction power during running of the magnetic tape for a long time. The magnetic recording medium, in tape form, reproduces a magnetic recorded signal by a reproducing magnetic head utilizing a magnetoresistive effect element, and has a nonmagnetic layer including nonmagnetic powder dispersed in a binder, and a magnetic layer including ferromagnetic powder dispersed in a binder, the nonmagnetic layer and the magnetic layer are successively formed on a long tape-like nonmagnetic substrate, wherein the nonmagnetic layer contains the nonmagnetic powder having pH of 7.5 or more, and wherein the nonmagnetic layer or/and the magnetic layer contain at least one fatty acid amide having an alkyl group having 8 or more carbon atoms.
    Type: Application
    Filed: October 22, 2004
    Publication date: April 28, 2005
    Inventors: Yasuhiro Nishida, Takamitsu Harada, Minoru Yamaga
  • Patent number: 6162730
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping or grinding step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 5904568
    Abstract: A process for precisely and efficiently manufacturing a semiconductor wafer is provided, which can prevent contamination by metals inside silicon crystals and remove the factors that degrade the GOI produced during the wafer manufacturing steps. A sliced and chamfered semiconductor wafer is subjected to lapping. The lapped semiconductor wafer is then etched, and thus the working strains produced by lapping is removed. The two sides of the etched semiconductor wafer are then primary polished with a dual-surface polishing machine. The primary polished semiconductor wafer is etched with an aqueous solution of 1% NaOH solution. The weak alkali etched semiconductor wafer is then mirror processed by a finish polishing. The finish polished semiconductor wafer is washed with an SC-1 solution.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: May 18, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Masahiko Maeda, Takamitsu Harada, Hisami Motoura, Eiichi Asano
  • Patent number: 5899743
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 4, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 5849636
    Abstract: A method processes a semiconductor wafer by etching the wafer, which has been smoothed by rough lapping, with alkaline solution. A rod is sliced into a plurality of wafers. The peripheral edges of the wafers are chamfered. The processed strain layers over the wafers due to chamfering are smoothed and planarized. The processed strain layers are then removed by etching with alkaline solution. The etched wafers are mirror polished. Lastly, the mirror-polished wafers are cleaned.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Takamitsu Harada, Kouichi Imura, Hisaya Fukunaga, Masahiko Maeda