Patents by Inventor Takamitsu Hattori

Takamitsu Hattori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923492
    Abstract: An apparatus for manufacturing a bagged electrode includes a conveying unit, a first bonding unit, a second bonding unit, and a separating unit. The conveying unit conveys an electrode in a manner interposed between a pair of long separator materials unwound from a pair of rolls. The first bonding unit bonds the pair of long separator materials outside the electrode along a conveyance direction without stopping conveyance of the electrode and the pair of long separator materials. The second bonding unit bonds the pair of long separator materials outside the electrode along a direction intersecting the conveyance direction without stopping conveyance of the electrode and the pair of long separator materials. The separating unit cuts the pair of long separator materials along the direction intersecting the conveyance direction to cut off the bagged electrode without stopping conveyance of the electrode and the pair of long separator materials.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 5, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kobayashi, Misato Ishikawa, Shunsuke Hattori, Takamitsu Sunaoshi, Takahiro Kokubo
  • Publication number: 20220177531
    Abstract: Provided are proteins or peptides, which may be referred to as monobodies. Fusion proteins and proteolysis targeting chimeras (PROTACs) comprising the proteins or peptides are also provided. Also provided are compositions of the proteins or peptides of the present disclosure, as well as compositions of fusion proteins and compositions of PROTACs. Methods of treating an individual in need of treatment are also provided. The methods may be to treat an individual suffering from or suspected of having KRAS(G12V), KRAS(G12S), KRAS(G12A) and/or KRAS(G12C)-associated cancers. A method may be for inhibiting ERK activation and/or proliferation of KRAS(G12V), KRAS(G12S), KRAS(G12A) and/or KRAS(G12C)-associated cancers.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 9, 2022
    Inventors: Shohei Koide, Kai Wen Teng, Akiko Koide, Takamitsu Hattori
  • Publication number: 20220073612
    Abstract: Disclosed herein are antibodies specific to a delta-1 chain of a ?? T cell receptor and methods of using such for modulating ?? T cell bioactivity. Such anti-Delta 1 antibodies may also be used to treat diseases associated with ?? T cell activation, such as solid tumors, or for detecting presence of ??1 T cells.
    Type: Application
    Filed: January 23, 2020
    Publication date: March 10, 2022
    Inventors: Shohei KOIDE, George MILLER, Akiko KOIDE, Tatyana PANCHENKO, Takamitsu HATTORI, Aleksandra FILIPOVIC, Eric ELENKO, Joseph BOLEN
  • Patent number: 10667391
    Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. Each build-up layer includes a first insulating layer including reinforcing material, a second resin insulating layer not containing reinforcing material, a first via conductor through the first insulating layer, and a second via conductor through the second insulating layer such that the top diameter of the first via conductor is substantially equal to the top diameter of the second via conductor and that the bottom diameter of the first via conductor is smaller than the bottom diameter of the second via conductor. The conductor layer on the first insulating layer includes a metal foil, a seed layer and an electrolytic plating film. The conductor layer on the second insulating-layer includes a seed layer and an electrolytic plating film and has thickness substantially equal to thickness of the conductor layer on the first insulating-layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 26, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Naohito Ishiguro, Takamitsu Hattori
  • Publication number: 20190394877
    Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. Each build-up layer includes a first insulating layer including reinforcing material, a second resin insulating layer not containing reinforcing material, a first via conductor through the first insulating layer, and a second via conductor through the second insulating layer such that the top diameter of the first via conductor is substantially equal to the top diameter of the second via conductor and that the bottom diameter of the first via conductor is smaller than the bottom diameter of the second via conductor. The conductor layer on the first insulating layer includes a metal foil, a seed layer and an electrolytic plating film. The conductor layer on the second insulating-layer includes a seed layer and an electrolytic plating film and has thickness substantially equal to thickness of the conductor layer on the first insulating-layer.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohito ISHIGURO, Takamitsu HATTORI
  • Patent number: 10208110
    Abstract: Embodiments concern compositions and methods involving recombinant antibodies to histone post-translational modifications. The invention provides compositions and methods for histone methyltransferase assays. In certain embodiments, the compositions and methods involve a recombinant antibody that binds histone H3 fragment harboring biomarkers such as H3K9me3 mark, H3K4me3 mark, H3K36me3 mark, H3K27me3, H3K9me3 and H3S10phos or a recombinant antibody that binds histone H4 fragment harboring H4K20me3 mark.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 19, 2019
    Assignee: The University of Chicago
    Inventors: Takamitsu Hattori, Shohei Koide, Joseph Taft, Akiko Koide
  • Publication number: 20140116769
    Abstract: A printed wiring board including an insulative material, a first conductive circuit formed on the insulative material, a resin insulation layer including a first insulation layer formed on the insulative material and on the first conductive circuit and which insulates between lines of the first conductive circuit, the first insulation layer including inorganic particles having a first average diameter, and a second insulation layer formed on the first insulation layer and including a recessed portion and an opening portion, the second insulation layer including inorganic particles having a second average diameter smaller than the first average diameter, a second conductive circuit formed in the recessed portion, and a via conductor formed in the opening portion and which connects the first conductive circuit to the second conductive circuit.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoshinori TAKENAKA, TAKESHI NAKAMURA, TAKAMITSU HATTORI
  • Patent number: 8263878
    Abstract: A printed wiring board disperses stress throughout an inner conductor layer, ensuring the flatness of a substrate. Embedding wires into the outermost insulating layer and forming the wires in a tapered shape that widens downward reduces the amount of stress applied on the edge of the inner conductor layer. This also prevents cracks from forming within the insulating layer, while maintaining favorable yield rates. Via diameters may also be reduced to increase circuit density.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: September 11, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshinori Takenaka, Takeshi Nakamura, Takamitsu Hattori
  • Publication number: 20100006334
    Abstract: A printed wiring board including an insulative material, a first conductive circuit formed on the insulative material, a resin insulation layer including a first insulation layer formed on the insulative material and on the first conductive circuit and which insulates between lines of the first conductive circuit, the first insulation layer including inorganic particles having a first average diameter, and a second insulation layer formed on the first insulation layer and including a recessed portion and an opening portion, the second insulation layer including inorganic particles having a second average diameter smaller than the first average diameter, a second conductive circuit formed in the recessed portion, and a via conductor formed in the opening portion and which connects the first conductive circuit to the second conductive circuit.
    Type: Application
    Filed: June 2, 2009
    Publication date: January 14, 2010
    Applicant: IBIDEN CO., LTD
    Inventors: Yoshinori TAKENAKA, Takeshi NAKAMURA, Takamitsu HATTORI
  • Publication number: 20090242261
    Abstract: A printed wiring board disperses stress throughout an inner conductor layer, ensuring the flatness of a substrate. Embedding wires into the outermost insulating layer and forming the wires in a tapered shape that widens downward reduces the amount of stress applied on the edge of the inner conductor layer. This also prevents cracks from forming within the insulating layer, while maintaining favorable yield rates. Via diameters may also be reduced to increase circuit density.
    Type: Application
    Filed: January 16, 2009
    Publication date: October 1, 2009
    Applicant: IBIDEN CO., LTD
    Inventors: Yoshinori Takenaka, Takeshi Nakamura, Takamitsu Hattori