Patents by Inventor Takamitsu Noda

Takamitsu Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11699692
    Abstract: A semiconductor device includes a first switching element, a second switching element, an optical coupling element, a plurality of leads and an outer resin member. The first switching element includes a first semiconductor chip and a first inner resin member sealing the first semiconductor chip. The second switching element includes a second semiconductor chip and a second inner resin member sealing the second semiconductor chip. The optical coupling element includes a light-emitting element, a light-receiving element and a third inner resin member sealing the light-emitting element and the light-receiving element. The first and second switching element and the optical coupling element are provided with terminals projecting from the first to third inner resin member, and the plurality of leads are electrically connected to the terminals. The outer resin member seals the first and second switching elements, the optical coupling element, and the plurality of leads.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: July 11, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Takamitsu Noda
  • Patent number: 11402591
    Abstract: An optical coupling device of an embodiment includes: a first lead frame; a light emitting element provided on the first lead frame; a second lead frame; a light receiving element provided on the second lead frame and facing the light emitting element; a polyimide resin covering a light emitting surface of the light emitting element; a transparent resin portion provided between the light emitting element and the light receiving element; and a light-shielding resin molded body accommodating the light emitting element and the light receiving element.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 2, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takamitsu Noda, Yoshiko Takahashi
  • Publication number: 20210398962
    Abstract: A semiconductor device includes a first switching element, a second switching element, an optical coupling element, a plurality of leads and an outer resin member. The first switching element includes a first semiconductor chip and a first inner resin member sealing the first semiconductor chip. The second switching element includes a second semiconductor chip and a second inner resin member sealing the second semiconductor chip. The optical coupling element includes a light-emitting element, a light-receiving element and a third inner resin member sealing the light-emitting element and the light-receiving element. The first and second switching element and the optical coupling element are provided with terminals projecting from the first to third inner resin member, and the plurality of leads are electrically connected to the terminals. The outer resin member seals the first and second switching elements, the optical coupling element, and the plurality of leads.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 23, 2021
    Inventor: Takamitsu NODA
  • Publication number: 20210294049
    Abstract: An optical coupling device of an embodiment includes: a first lead frame; a light emitting element provided on the first lead frame; a second lead frame; a light receiving element provided on the second lead frame and facing the light emitting element; a polyimide resin covering a light emitting surface of the light emitting element; a transparent resin portion provided between the light emitting element and the light receiving element; and a light-shielding resin molded body accommodating the light emitting element and the light receiving element.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 23, 2021
    Inventors: Takamitsu Noda, Yoshiko Takahashi
  • Publication number: 20150235937
    Abstract: The suppression of resin leakage is combined with the suppression of damage to the functional wiring area of a wiring board in forming an encapsulation resin. A method for manufacturing a semiconductor device includes the step of clamping a wiring board with a first mold and a second mold. The second mold includes: a flat portion contacting a wiring board; a recessed portion forming a cavity to form an encapsulation resin; and a projecting portion formed at a location spaced apart from the recessed portion on the flat portion, the projecting portion projecting on the first mold side, and extending along the first edge of the wiring board.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventor: Takamitsu Noda
  • Patent number: 9087826
    Abstract: The suppression of resin leakage is combined with the suppression of damage to the functional wiring area of a wiring board in forming an encapsulation resin. A method for manufacturing a semiconductor device includes the step of clamping a wiring board with a first mold and a second mold. The second mold includes: a flat portion contacting a wiring board; a recessed portion forming a cavity to form an encapsulation resin; and a projecting portion formed at a location spaced apart from the recessed portion on the flat portion, the projecting portion projecting on the first mold side, and extending along the first edge of the wiring board.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: July 21, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takamitsu Noda
  • Publication number: 20130256851
    Abstract: The suppression of resin leakage is combined with the suppression of damage to the functional wiring area of a wiring board in forming an encapsulation resin. A method for manufacturing a semiconductor device includes the step of clamping a wiring board with a first mold and a second mold. The second mold includes: a flat portion contacting a wiring board; a recessed portion forming a cavity to form an encapsulation resin; and a projecting portion formed at a location spaced apart from the recessed portion on the flat portion, the projecting portion projecting on the first mold side, and extending along the first edge of the wiring board.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 3, 2013
    Applicant: Renesas Electronics Corporation
    Inventor: Takamitsu Noda
  • Patent number: 8053337
    Abstract: In a method of manufacturing a semiconductor device, a first groove and a second groove each having a width less than that of a scribe line are formed along the scribe line in a first protective film provided below a second protective film which protects element forming regions when a wafer is divided into parts by a laser dicing, and the first groove and the second groove are filled with the second protective film. Then, the laser dicing is performed on a region between the first groove and the second groove along the scribe line from the surface where the second protective film is formed to form a cutting groove that reaches at least a predetermined depth of the multi-layer interconnect.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takamitsu Noda
  • Patent number: 7888809
    Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Miyagawa, Takamitsu Noda, Hiroyasu Miyamoto, Jun Tsukano
  • Publication number: 20100273312
    Abstract: In a method of manufacturing a semiconductor device, a first groove and a second groove each having a width less than that of a scribe line are formed along the scribe line in a first protective film provided below a second protective film which protects element forming regions when a wafer is divided into parts by a laser dicing, and the first groove and the second groove are filled with the second protective film. Then, the laser dicing is performed on a region between the first groove and the second groove along the scribe line from the surface where the second protective film is formed to form a cutting groove that reaches at least a predetermined depth of the multi-layer interconnect.
    Type: Application
    Filed: March 26, 2010
    Publication date: October 28, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takamitsu Noda
  • Patent number: 7759223
    Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: July 20, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Tsuyoshi Kida, Takamitsu Noda
  • Publication number: 20100176517
    Abstract: Differences in contraction forces of a sealing resin can be alleviated and strain on a package can be reduced even when electronic components are unevenly positioned on a substrate. An electronic device (100) includes a substrate 102, electronic components (104, 108) mounted on one face of the substrate 102, and a sealing resin 118 formed on the one face of the substrate 102 and which seals the electronic components. The sealing resin 118 includes a first resin region 120 made up of a first resin composition and a second resin region 122 made up of a second resin composition, and is formed so as to have, as seen in planar view, a region in which only the first resin region 120 exists and a region in which only the second resin region 122 exists.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 15, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Jun Tsukano, Kenji Furuya, Takamitsu Noda, Hiroyasu Miyamoto
  • Publication number: 20100102461
    Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 29, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Takamitsu Noda, Hiroyasu Miyamoto, Jun Tsukano
  • Publication number: 20090227088
    Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
    Type: Application
    Filed: May 13, 2009
    Publication date: September 10, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tsuyoshi KIDA, Takamitsu Noda
  • Patent number: 7554211
    Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: June 30, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tsuyoshi Kida, Takamitsu Noda
  • Publication number: 20050282360
    Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 22, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tsuyoshi Kida, Takamitsu Noda