Abstract: An integrated circuit including a signal line layout is disclosed. A signal line layout may include a number of signal lines configured for conveying a number of signals. The signal line layout may further include a number of shield lines. Each signal line of the number of signal lines may be positioned adjacent a first shield line and a second shield line of the number of the shield lines. Further, first shield line may extend a length of an adjacent signal line and the second shield line may extend less than a length of the adjacent signal line. An electronic system including circuitry having one or more signal line layouts, and methods of forming signal line layout are also described.

Abstract: Apparatuses for providing a clock signal for a plurality of circuits of a semiconductor device within delays in a certain range are described. An example apparatus includes a signal wire including a first portion and a second portion, having one ends coupled to each other at a signal input and the other ends coupled to each other that extend in parallel. The second portion has a higher impedance than the first portion from the first end to the second end. Output buffers closer to the signal input are coupled to the second portion and output buffers farther to the signal input are coupled to the first portion.

Abstract: Apparatuses for providing a clock signal for a plurality of circuits of a semiconductor device within delays in a certain range are described. An example apparatus includes a signal wire including a first portion and a second portion, having one ends coupled to each other at a signal input and the other ends coupled to each other that extend in parallel. The second portion has a higher impedance than the first portion from the first end to the second end. Output buffers closer to the signal input are coupled to the second portion and output buffers farther to the signal input are coupled to the first portion.

Abstract: An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and second output transistors coupled correspondingly to the first and second data pads and arranged adjacently to each other in the first direction and at least one contact plug through which a voltage is supplied to each of the first and second output transistors. The at least one contact plug is arranged between the first and second output transistors.

Abstract: An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and second output transistors coupled correspondingly to the first and second data pads and arranged adjacently to each other in the first direction and at least one contact plug through which a voltage is supplied to each of the first and second output transistors. The at least one contact plug is arranged between the first and second output transistors.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

Abstract: A semiconductor device is disclosed, which comprises first and second input ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node.

Abstract: A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A semiconductor device is disclosed, which comprises First and second inputs ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node.

Abstract: A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

Abstract: A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

Abstract: A semiconductor device of the invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage lower than the power supply voltage, a ground voltage and a sub-ground voltage higher than the ground voltage are supplied; a main power supply line supplying the power supply voltage; and a main ground line supplying the ground voltage. A unit circuit constituting the logic circuit includes first to third PMOS transistors and first to third PMOS transistors. The third PMOS transistor is connected between sources of the first and second PMOS transistors, the main power supply line is connected to its one node, and the sub-power supply voltage is generated at its other node. The third NMOS transistor is connected between sources of the first and second NMOS transistors, the main ground line is connected to its one node, and the sub-ground voltage is generated at its other node.

Abstract: A semiconductor device which can prevent damage to an ESD protection device by pressure when bonding is carried out, while having a pad configuration that can ensure bonding reliability, with the semiconductor device being made as small as possible. A bonding area that is an area for wire bonding with respect to an external electrode pad and a probing area that is an area in which a probe needle is applied when probing, are provided, and the ESD protection device and a discharge path therefor are arranged below the probing area. Arranged below the bonding area are a support via that is a little smaller than the bonding pad, and a support pattern having a size corresponding to the bonding pad and joined to the bonding pad by the support via.

Abstract: A semiconductor device of the invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage lower than the power supply voltage, a ground voltage and a sub-ground voltage higher than the ground voltage are supplied; a main power supply line supplying the power supply voltage; and a main ground line supplying the ground voltage. A unit circuit constituting the logic circuit includes first to third PMOS transistors and first to third PMOS transistors. The third PMOS transistor is connected between sources of the first and second PMOS transistors, the main power supply line is connected to its one node, and the sub-power supply voltage is generated at its other node. The third NMOS transistor is connected between sources of the first and second NMOS transistors, the main ground line is connected to its one node, and the sub-ground voltage is generated at its other node.