Abstract: A data processing system having hierarchical memories comprised of buffer memories contained in a plurality of central processing units, an intermediate buffer memory and a main memory having a plurality of banks. The intermediate buffer memory and the main memory are controlled under both a swap control method and a set associative control method. These two memories are accessed by address information which includes both bank-selection address bits and set-selection address bits. The bank-selection address bits are partially modified by part of the set-selection address bits.

Abstract: A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.

Abstract: An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.

Abstract: A printed board comprising a plurality of through holes formed therein and located on intersecting points of an X-Y orthogonal basic grid, and an oblique conductor pattern, wherein conductors are formed along channels arranged in accordance with a principle that one conductor passes between adjacent grid points arranged in the X direction, while two or more conductors pass between adjacent grid points arranged in the Y direction, and each conductor obliquely extends in a zigzag line without contacting the grid points. Such conductor pattern ensures a high density and minimum length of wiring.

Abstract: An electronic device which includes at least one semiconductor chip with at least one circuit element thereon and connection patterns thereon being connected to the circuit element or elements. The connection patterns comprise a lower connection pattern, which is standardized and widely applicable to many kinds of circuits, and an upper connection pattern, which is positioned on the upper side of said lower connection pattern. The upper connection pattern and the lower connection pattern are connected in conformity with the desired circuit to be obtained.

Abstract: In a data processing system having an intermediate buffer memory provided between a large space main memory and small space, high speed buffer memories of a plurality of processors, a data block of the intermediate buffer memory to be replaced with a data block of the main memory is determined by utilizing LRU (Least Recently Used) algorithm as well as copy flags employed in buffer invalidation processing. In the intermediate buffer memory, a data block that the number of its copy flags in the ON state is smaller than any other data blocks, is selected as the data block to be replaced. The fact that the number of copy flags in the ON state implies that the data block is not frequently used by the processors. Replacement of such a data block alleviates the burden of the buffer invalidation processing imposed on the intermediate buffer memory.

Abstract: A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode.