Abstract: A multicore processor has a plurality of processor cores each of which is configured to execute a computation, a plurality of reconfigurable devices dynamically reconfigurable in circuit configuration on the basis of circuit information, and a lock state storage section configured to store lock information indicating whether or not each of the reconfigurable devices is locked. The multicore processor also has a plurality of reconfigurable control sections each of which is configured to load circuit information for a computation to be executed into one of the reconfigurable devices not locked, by referring to the lock information, performs execution of the computation with the reconfigurable device and execution of the computation with the one of the processor cores in parallel with each other, and perform control so that results of execution of the computation completed faster are adopted.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: In hyperframe synchronization processing of a hyperframe including FEXT frames and NEXT frames, each difference between the number of consecutive FEXT frames and the number of consecutive NEXT frames is calculated, and a unique sequence of these differences is detected. When the unique sequence of differences can be detected from a received hyperframe, the position of a frame which is being received now in the hyperframe can be specified at that point in time. Hence, hyperframe synchronization can be established in a short time after frame synchronization is established.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: In hyperframe synchronization processing of a hyperframe including FEXT frames and NEXT frames, each difference between the number of consecutive FEXT frames and the number of consecutive NEXT frames is calculated, and a unique sequence of these differences is detected. When the unique sequence of differences can be detected from a received hyperframe, the position of a frame which is being received now in the hyperframe can be specified at that point in time. Hence, hyperframe synchronization can be established in a short time after frame synchronization is established.

Abstract: A model of architecture of a processor is called an architecture template. Because a designer selects an architecture template of a special purpose processor which is suitable for an objective signal processing algorithm from an architecture template library, a special purpose processor which is the most suitable for any signal algorithm can be synthesized. Moreover, by providing a method of creating an architecture template simply, even if there is no desirable architecture template, an objective architecture template can be synthesized for a short time.