Patents by Inventor Takane YAMADA

Takane YAMADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187221
    Abstract: Provided is a semiconductor device manufacturing method including a process of annealing a semiconductor wafer in a state in which a supported portion on a lower surface of the semiconductor wafer is supported by using a supporting portion, wherein the supported portion includes one or a plurality of supporting portions and the supporting portion includes one or a plurality of supporting portions, the method comprising: forming impurity regions including a first impurity in a region which is overlapped with the supported portion in a top view and which is apart from an edge of the semiconductor wafer; annealing the semiconductor wafer in a state in which the lower surface of the semiconductor wafer is supported by the supporting portion; and removing the impurity regions by removing a region including the lower surface of the semiconductor wafer.
    Type: Application
    Filed: October 20, 2022
    Publication date: June 15, 2023
    Inventors: Takane YAMADA, Masayuki MOMOSE, Naoki KUNESHITA