Patents by Inventor Takanobu Itoh
Takanobu Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10797077Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: December 3, 2019Date of Patent: October 6, 2020Assignee: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Publication number: 20200111809Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: December 3, 2019Publication date: April 9, 2020Applicant: Toshiba Memory CorporationInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
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Patent number: 10541251Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: July 23, 2018Date of Patent: January 21, 2020Assignee: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Patent number: 10490466Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.Type: GrantFiled: January 24, 2018Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Kazumasa Ito, Seiichi Omoto, Takanobu Itoh, Ryota Nakanishi
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Publication number: 20180350834Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: July 23, 2018Publication date: December 6, 2018Applicant: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Patent number: 10074665Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: September 6, 2016Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Genki Kawaguchi, Masanori Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Publication number: 20180151457Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.Type: ApplicationFiled: January 24, 2018Publication date: May 31, 2018Applicant: Toshiba Memory CorporationInventors: Kazumasa ITO, Seiichi OMOTO, Takanobu ITOH, Ryota NAKANISHI
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Publication number: 20170077108Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: September 6, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
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Publication number: 20170062286Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.Type: ApplicationFiled: February 3, 2016Publication date: March 2, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa ITO, Seiichi Omoto, Takanobu Itoh, Ryota Nakanishi
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Publication number: 20160322379Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, a charge accumulation layer, and a contact. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end thereof connected to the substrate, has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The contact has its lower end connected to the substrate, and has its lower end and its upper end configured from a metal silicide.Type: ApplicationFiled: September 9, 2015Publication date: November 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takao OOMORI, Takanobu ITOH, Hisataka MEGURO, Hideaki HARAKAWA
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Patent number: 6605361Abstract: A coating composition that can be applied to a lens, a method of making the coating composition, and a coated lens comprising a cured coating composition of the invention are disclosed. The coating composition is produced by providing a mixture comprising metal oxide colloid particles and an organosilicon compound, and adding an acetylacetonate metal salt and an aliphatic amine to the mixture.Type: GrantFiled: October 1, 2001Date of Patent: August 12, 2003Assignee: Hoya CorporationInventors: Jun Watanabe, Takanobu Itoh
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Publication number: 20020064665Abstract: A coating composition that can be applied to a lens, a method of making the coating composition, and a coated lens comprising a cured coating composition of the invention are disclosed. The coating composition is produced by providing a mixture comprising metal oxide colloid particles and an organosilicon compound, and adding an acetylacetonate metal salt and an aliphatic amine to the mixture.Type: ApplicationFiled: October 1, 2001Publication date: May 30, 2002Inventors: Jun Watanabe, Takanobu Itoh
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Patent number: 6306513Abstract: An optical element having, on an optical substrate, a cured film formed of a coating agent containing (A) modified stannic oxide-zirconium oxide composite colloid particles as prepared by coating at least a part of the surfaces of stannic oxide-zirconium oxide composite colloid particles with stannic oxide-tungsten oxide-silicon oxide composite colloid particles, and (B) an organosilicon compound.Type: GrantFiled: March 30, 2000Date of Patent: October 23, 2001Assignee: Hoya CorporationInventors: Takanobu Itoh, Keitaro Suzuki, Yoshinari Koyama, Motoko Iijima
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Patent number: 4607878Abstract: A synthetic resin body panel for mounting on a skeletal automobile body to cover the entire door sill and the front lower portion of the rear fender with the front edge offset inwardly to be clamped between the front fender and auto body to allow movement for thermal expansion and contraction. A sealing member is clamped between the rearmost portion of the panel and the skeletal body of the rear fender for preventing water, pebbles, etc. from entering the space between the panel and body.Type: GrantFiled: June 14, 1984Date of Patent: August 26, 1986Assignee: Honda Giken Kogyo Kabushiki KaishaInventor: Takanobu Itoh