Patents by Inventor Takanobu Itoh

Takanobu Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797077
    Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 6, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
  • Publication number: 20200111809
    Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 9, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
  • Patent number: 10541251
    Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
  • Patent number: 10490466
    Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazumasa Ito, Seiichi Omoto, Takanobu Itoh, Ryota Nakanishi
  • Publication number: 20180350834
    Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
  • Patent number: 10074665
    Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Genki Kawaguchi, Masanori Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
  • Publication number: 20180151457
    Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.
    Type: Application
    Filed: January 24, 2018
    Publication date: May 31, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kazumasa ITO, Seiichi OMOTO, Takanobu ITOH, Ryota NAKANISHI
  • Publication number: 20170077108
    Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
  • Publication number: 20170062286
    Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.
    Type: Application
    Filed: February 3, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa ITO, Seiichi Omoto, Takanobu Itoh, Ryota Nakanishi
  • Publication number: 20160322379
    Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, a charge accumulation layer, and a contact. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end thereof connected to the substrate, has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The contact has its lower end connected to the substrate, and has its lower end and its upper end configured from a metal silicide.
    Type: Application
    Filed: September 9, 2015
    Publication date: November 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao OOMORI, Takanobu ITOH, Hisataka MEGURO, Hideaki HARAKAWA
  • Patent number: 6605361
    Abstract: A coating composition that can be applied to a lens, a method of making the coating composition, and a coated lens comprising a cured coating composition of the invention are disclosed. The coating composition is produced by providing a mixture comprising metal oxide colloid particles and an organosilicon compound, and adding an acetylacetonate metal salt and an aliphatic amine to the mixture.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: August 12, 2003
    Assignee: Hoya Corporation
    Inventors: Jun Watanabe, Takanobu Itoh
  • Publication number: 20020064665
    Abstract: A coating composition that can be applied to a lens, a method of making the coating composition, and a coated lens comprising a cured coating composition of the invention are disclosed. The coating composition is produced by providing a mixture comprising metal oxide colloid particles and an organosilicon compound, and adding an acetylacetonate metal salt and an aliphatic amine to the mixture.
    Type: Application
    Filed: October 1, 2001
    Publication date: May 30, 2002
    Inventors: Jun Watanabe, Takanobu Itoh
  • Patent number: 6306513
    Abstract: An optical element having, on an optical substrate, a cured film formed of a coating agent containing (A) modified stannic oxide-zirconium oxide composite colloid particles as prepared by coating at least a part of the surfaces of stannic oxide-zirconium oxide composite colloid particles with stannic oxide-tungsten oxide-silicon oxide composite colloid particles, and (B) an organosilicon compound.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 23, 2001
    Assignee: Hoya Corporation
    Inventors: Takanobu Itoh, Keitaro Suzuki, Yoshinari Koyama, Motoko Iijima
  • Patent number: 4607878
    Abstract: A synthetic resin body panel for mounting on a skeletal automobile body to cover the entire door sill and the front lower portion of the rear fender with the front edge offset inwardly to be clamped between the front fender and auto body to allow movement for thermal expansion and contraction. A sealing member is clamped between the rearmost portion of the panel and the skeletal body of the rear fender for preventing water, pebbles, etc. from entering the space between the panel and body.
    Type: Grant
    Filed: June 14, 1984
    Date of Patent: August 26, 1986
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventor: Takanobu Itoh