Abstract: A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

Abstract: A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

Abstract: A received frame processing device that receives a frame of variable length from a network, and transfers the frame to a buffer group that is provided on a system memory and is a common area to a CPU, wherein a buffer includes a plurality of buffers. And a second frame is transferred to a first buffer when the second frame is received before a given amount of time has elapsed after a first frame has been transferred to the first buffer, on the other hand, the second frame is transferred to a second buffer after the ownership of the first buffer has been transferred to the CPU when the second frame is received after the first frame has been transferred to the first buffer and after a given amount of time or longer has elapsed.