Patents by Inventor Takanobu Nakagawa

Takanobu Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220317052
    Abstract: A detecting device is provided; which includes: a substrate; a plurality of photo sensors disposed on the substrate; and a stress luminescent layer disposed on at least one of the plurality of photo sensors.
    Type: Application
    Filed: April 2, 2021
    Publication date: October 6, 2022
    Inventor: Takanobu NAKAGAWA
  • Patent number: 5614729
    Abstract: A transparent insulation film is formed on a glass substrate. Source and drain electrodes are formed on the transparent insulation film with their ends in spaced and opposing relation. The entire face of the substrate is treated with PH.sub.3 plasma to diffuse P atoms to form a doped surface layer. An a-Si semiconductor layer is formed on the doped surface layer so as to span a space between the source and drain electrodes with the opposite end portions of the semiconductor layer overlying those electrodes. A gate insulation film is formed on the semiconductor layer to extend all over the substrate. A gate electrode is formed of metal on the top of the gate insulation film 6 such that the opposite side edges of the gate electrode are recessed inwardly of the edges of the source and drain electrodes. An excimer laser beam is radiated against the face of the substrate with the gate electrode acting as a mask so that the laser-irradiated regions of the semiconductor layer comprise source and drain regions of n.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: March 25, 1997
    Assignee: Hosiden Corporation
    Inventors: Yasuhiro Ukai, Tomihisa Sunata, Takanobu Nakagawa, Shu Takeuchi
  • Patent number: 5576863
    Abstract: Liquid crystal is encapsulated between two transparent substrates 16, 17. Pixel electrodes 13 are formed on the inner surface of the transparent substrate 17 in the form of a matrix while a common electrode 12 is formed on the inner surface of the transparent substrate 16. Each pixel electrode 13 is divided into subpixel electrodes 13.sub.1, 13.sub.2. The subpixel electrode 13.sub.1 is connected to the drain of a thin film transistor 21 formed adjacent the subpixel electrode to apply driving voltage to the electrode. The subpixel electrode 13.sub.2 is supplied with capacitance-divided driving voltage through a capacitor comprising the electrode 13.sub.1, and a control capacitor 15 connected thereto with an insulation layer 14 interposed therebetween. Each of the subpixel electrodes 13.sub.1, 13.sub.2 are divided into two domains on which are formed alignment layers 41a, 41b, 42a, 42b, in opposition to alignment layers 43a, 43b, 44a, 44b formed on the common electrode 12.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: November 19, 1996
    Assignee: Hosiden Corporation
    Inventors: Shigeo Aoki, Yasuhiro Ukai, Tomihisa Sunata, Takanobu Nakagawa, Minoru Shibazaki
  • Patent number: 5162933
    Abstract: In an active matrix structure for liquid crystal display elements which includes pixel electrodes arranged in a matrix form on a glass base plate, thin film transistors having their drains connected to the pixel electrodes, respectively, data lines each connected to sources of the thin film transistors of one column and gate lines connected to gates of the thin film transistors of one row, there are provided in the same plane a light blocking layer disposed opposite each of the thin film transistors across an insulating layer, a storage capacitance electrode disposed partly opposite each of the pixel electrodes across the insulating layer and storage capacitance lines for interconnecting the capacitance electrodes. The light blocking layers, the storage capacitance electrodes and the storage capacitance lines are formed of the same material and at the same time.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: November 10, 1992
    Assignees: Nippon Telegraph and Telephone Corporation, Hosiden Corporation
    Inventors: Nobuhiko Kakuda, Tsutomu Wada, Kinya Kato, Tadamichi Kawada, Masamichi Okamura, Shigeo Aoki, Yasuhiro Ukai, Kiyoshi Taruta, Tomihisa Sunata, Hiroshi Saito, Takanobu Nakagawa