Patents by Inventor Takanobu Ono
Takanobu Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12230623Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of recess portions on a first surface of a support. Each recess portion is between protrusion portions on the first surface. A stacked body is then placed into each of the recess portions. The stacked body is a plurality of semiconductor chips stacked on each other or the like. The recess portions are filled with a resin layer. The resin layer covers the stacked bodies inside the recess portions. A protrusion portion of the support is irradiated with a laser beam to form a modified portion in the protrusion portion. The support is divided along the protrusion portions into separate pieces.Type: GrantFiled: February 28, 2022Date of Patent: February 18, 2025Assignee: Kioxia CorporationInventors: Masaki Sekine, Takanobu Ono
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Patent number: 12185547Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: GrantFiled: September 19, 2023Date of Patent: December 31, 2024Assignee: KIOXIA CORPORATIONInventors: Takanobu Ono, Yusuke Dohmae
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Patent number: 11966679Abstract: An information processing apparatus includes a processor connected to a programmable logic circuit and configured to: acquire a software module indicating first processing and start the first processing; reconfigure a hardware module in the programmable logic circuit, the hardware module indicating second processing included in the first processing; and, if reconfiguration of the hardware module is completed before the first processing is completed, supply intermediate data generated by the first processing to the hardware module and cause the programmable logic circuit to start to execute the second processing.Type: GrantFiled: May 25, 2021Date of Patent: April 23, 2024Assignee: FUJIFILM Business Innovation Corp.Inventor: Takanobu Ono
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Patent number: 11930623Abstract: A board structure includes: a board with a heat generating element; a heat sink including a plate-shaped base member with one face contacting the heat generating element, and plural fins side by side on another face of the base member, the fins extending in a cooling air flow direction, the fins having distal ends downstream in the flow direction; a first resisting member on a downstream side with respect to the heat sink and acting as a resistor for exhaust of the cooling air; and a second resisting member on the downstream side and on a first side that the fins are arranged respective to the heat sink and acting as a resistor for the cooling air. Distal ends of the fins on a second side that the fins are arranged are upstream of the distal ends of the fins on the first side.Type: GrantFiled: December 1, 2021Date of Patent: March 12, 2024Assignee: FUJIFILM Business Innovation Corp.Inventor: Takanobu Ono
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Publication number: 20240071789Abstract: According to one embodiment, a semiconductor manufacturing apparatus includes a plurality of clamping portions and a control unit. Each of the plurality of clamping portions has a first rotating body and a second member. The clamping portions clamp a sheet on which a wafer is mounted. The clamping portions are positioned around an circumferential position of the wafer. The control unit controls rotation of each first rotating body of the plurality of clamping portions to pull the sheet outwardly to increase the distance between individualized chips of the wafer.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shoma OMURA, Takanobu ONO
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Publication number: 20240071826Abstract: A position determining method according to the present embodiment is a position determining method of a wafer which has a plurality of singulated chips and which is pasted on a tape. In addition, the present position determining method includes irradiating, with light, the wafer which has a first cut mark provided between the chips and a second cut mark with a width that differs from a width of the first cut mark. Furthermore, the present position determining method includes receiving irradiated light at a position opposing an irradiation position of light across the wafer. In addition, the present position determining method includes determining a position of the wafer based on a width of received light having passed through the wafer.Type: ApplicationFiled: August 2, 2023Publication date: February 29, 2024Applicant: Kioxia CorporationInventor: Takanobu ONO
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Publication number: 20240008277Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: ApplicationFiled: September 19, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Takanobu ONO, Yusuke DOHMAE
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Patent number: 11800709Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: GrantFiled: February 4, 2021Date of Patent: October 24, 2023Assignee: Kioxia CorporationInventors: Takanobu Ono, Yusuke Dohmae
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Publication number: 20230187279Abstract: A method for manufacturing a semiconductor device includes forming a first stacked body having a plurality of first material films and a plurality of second material films that are alternately stacked, in a divided region of a semiconductor wafer including a chip region in which a semiconductor element is provided and the divided region between the adjacent chip regions, a plurality of times in a normal line direction of a substrate surface of the semiconductor wafer. The semiconductor wafer is fragmented by a blade having a width wider than the width of the first stacked body.Type: ApplicationFiled: August 24, 2022Publication date: June 15, 2023Applicant: KIOXIA CORPORATIONInventors: Takanobu ONO, Masaki SEKINE, Kizashi TANIOKA, Takaaki AKAHANE
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Publication number: 20230058602Abstract: A board structure includes: a board provided with a heat generating element; a heat sink including a plate-shaped base member having one face being in contact with the heat generating element, and plural fins arranged side by side in a fin arrangement direction on an other face of the base member, the fins each extending in a flow direction in which cooling air flows, the fins each having a distal end at a downstream end in the flow direction; a first resisting member provided on a downstream side in the flow direction with respect to the heat sink, the first resisting member acting as a resistor for the cooling air to be exhausted; and a second resisting member provided on the downstream side in the flow direction and on a first side in the fin arrangement direction with respect to the heat sink, the second resisting member acting as a resistor for the cooling air to be exhausted.Type: ApplicationFiled: December 1, 2021Publication date: February 23, 2023Applicant: FUJIFILM BUSINESS INNOVATION CORP.Inventor: Takanobu ONO
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Patent number: 11551973Abstract: A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film.Type: GrantFiled: March 1, 2021Date of Patent: January 10, 2023Assignee: KIOXIA CORPORATIONInventors: Takanobu Ono, Keisuke Tokubuchi, Akira Tomono
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Publication number: 20220392883Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of recess portions on a first surface of a support. Each recess portion is between protrusion portions on the first surface. A stacked body is then placed into each of the recess portions. The stacked body is a plurality of semiconductor chips stacked on each other or the like. The recess portions are filled with a resin layer. The resin layer covers the stacked bodies inside the recess portions. A protrusion portion of the support is irradiated with a laser beam to form a modified portion in the protrusion portion. The support is divided along the protrusion portions into separate pieces.Type: ApplicationFiled: February 28, 2022Publication date: December 8, 2022Inventors: Masaki SEKINE, Takanobu Ono
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Publication number: 20220138390Abstract: An information processing apparatus includes a processor connected to a programmable logic circuit and configured to: acquire a software module indicating first processing and start the first processing; reconfigure a hardware module in the programmable logic circuit, the hardware module indicating second processing included in the first processing; and, if reconfiguration of the hardware module is completed before the first processing is completed, supply intermediate data generated by the first processing to the hardware module and cause the programmable logic circuit to start to execute the second processing.Type: ApplicationFiled: May 25, 2021Publication date: May 5, 2022Applicant: FUJIFILM Business Innovation Corp.Inventor: Takanobu ONO
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Patent number: 11309219Abstract: A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.Type: GrantFiled: March 5, 2020Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Akira Tomono, Keisuke Tokubuchi, Takanobu Ono
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Publication number: 20220059407Abstract: A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film.Type: ApplicationFiled: March 1, 2021Publication date: February 24, 2022Inventors: Takanobu ONO, Keisuke TOKUBUCHI, Akira TOMONO
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Patent number: 11139208Abstract: A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip.Type: GrantFiled: September 3, 2019Date of Patent: October 5, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takanobu Ono, Tsutomu Fujita, Ippei Kume, Akira Tomono
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Publication number: 20210167085Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: ApplicationFiled: February 4, 2021Publication date: June 3, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takanobu ONO, Yusuke DOHMAE
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Patent number: 11004743Abstract: According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. The method also includes detecting a second distance between a second portion of the substrate a second substrate information detection unit, the second portion different from the first portion. Distance information is calculated between the substrate and a processing lens, which is located farther from the second substrate information detection unit than from the first substrate information detection unit, based on the detected first distance and the detected second distance, and the substrate is irradiated with laser light from the processing lens based on the distance information.Type: GrantFiled: October 24, 2018Date of Patent: May 11, 2021Assignee: KIOXIA CORPORATIONInventors: Tsutomu Fujita, Takanobu Ono
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Publication number: 20210082761Abstract: A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.Type: ApplicationFiled: March 5, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Akira TOMONO, Keisuke Tokubuchi, Takanobu Ono
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Patent number: 10950621Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.Type: GrantFiled: February 26, 2019Date of Patent: March 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takanobu Ono, Yusuke Dohmae