Abstract: A timing analysis method includes performing voltage drop analysis of a circuit laid out on a semiconductor chip, creating a voltage drop region file representing voltage drop on the semiconductor chip as regions at given voltage ranges based on a result of the voltage drop analysis, calculating second OCV factors respectively corresponding to the given voltage ranges contained in the voltage drop region file for each of the regions by using an OCV factor file containing first OCV factors representing variation of delay in association with given voltages in consideration of voltage drop, creating an OCV region file containing the calculated second OCV factors and the regions in association with each other, performing delay calculation of the laid-out circuit by using a delay library, and performing timing analysis by using the delay calculation result and the second OCV factors for each of the regions contained in the OCV region file.

Abstract: A design support system including a data reading unit for reading circuit data for simulation of a circuit to be designed and analyzing and structuring the circuit data to output structured data, a structured circuit data storing unit for storing the structured circuit data output from the input data reading unit, and a circuit data editing unit for extracting and editing arbitrary part of data to be edited from the structured circuit data stored in the structured circuit data storing unit to merge the editing contents with the contents of the structured circuit data stored in the structured circuit data storing unit.