Abstract: A plant residue-decomposing agent comprising cells of Bacillus pumilus KS-C4 strain (FERM BP-10842), wherein the cells are formulated into the agent by using a liquid culture product of the KS-C4 strain as it is, or by concentrating the liquid culture product of the KS-C4 strain and then without separating the cells from a liquid.

Abstract: A method of producing Bacillus spores comprising a step of culturing the Bacillus bacterium using a liquid medium having a C/N ratio (weight ratio of carbon content to nitrogen content) of greater than 4 and less than 9.5.

Abstract: A method of producing Bacillus spores comprising a step of culturing the Bacillus bacterium using a liquid medium having a C/N ratio (weight ratio of carbon content to nitrogen content) of greater than 4 and less than 9.5.

Abstract: The present invention relates to a microbial pesticide composition, which is obtained by a method including the steps of: adjusting a pH of a culture solution of the Bacillus sp. bacterium to from 3.0 to 5.0 (pH adjustment step); mixing the culture solution with the calcium chloride and/or the magnesium sulfate (mixing step); and lyophilizing or spray-drying the culture solution (drying step). In the microbial pesticide composition, even if it is stored for a long period of time at room temperature, the active ingredient remains stable and a sufficient preventive effect against plant disease can be maintained.

Abstract: The present invention relates to a microbial pesticide composition, which is obtained by a method including the steps of: adjusting a pH of a culture solution of the Bacillus sp. bacterium to from 3.0 to 5.0 (pH adjustment step); mixing the culture solution with the calcium chloride and/or the magnesium sulfate (mixing step); and lyophilizing or spray-drying the culture solution (drying step). In the microbial pesticide composition, even if it is stored for a long period of time at room temperature, the active ingredient remains stable and a sufficient preventive effect against plant disease can be maintained.

Abstract: To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

Abstract: Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

Abstract: Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

Abstract: To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.