Abstract: A high speed pattern generator includes a programmable counter, n pattern generating circuits, a multiplexer and a control memory. The programmable counter divides a frequency of a system clock signal by n (n.gtoreq.2) to thereby generate a clock signal having a frequency of 1/n of the frequency of the system clock and a select signal representative of a count output of said programmable counter. The n pattern generating circuits operate at a frequency determined by the clock signal and produce a pattern signal as a function. A multiplexer converts patterns generated by the n pattern generating circuits into a time-serial pattern in response to the select signal for sequentially selecting outputs of the n pattern generating circuits to thereby output a fast pattern. A control memory which operates at a frequency determined by the clock signal produces a control signal to periodically switch a frequency division ratio of the programmable counter between a plurality of ratios.

Abstract: A timing signal generating apparatus is used for testing ICs, particularly ICs having more than two enable input terminals. Data representative of the time of occurrence of a timing signal with respect to a reference signal is stored in a memory. In a first cycle, data is combined by an arithmetic unit with data stored in another memory. The latter data represents a predetermined desired variation in the time of occurrence of the timing signal. The output of the arithmetic unit is then stored in a temporary memory and combined with the data representative of the predetermined variation in time of occurrence of the timing signal. The time of occurrence of the timing signal is determined by the output of the arithmetic unit. A timing signal is thus produced over an almost arbitrary range of delays with respect to the reference signal.

Abstract: A high-speed pattern generator includes a plurality of arithmetic and logic units (ALUs) which are n in number and have m-bit outputs, n registers receptive as inputs as outputs from the ALUs, and n-bit shift registers which are m in number, each ALU and connected register being unitized and coupled to the shift registers. The outputs of the registered input data are applied to the ALUs. The unitized ALUs and registers produce outputs applied in the same sequence to bits of the shift registers, which are responsive to clock pulses to generate a pattern output at a high speed.