Patents by Inventor Takanori Hiramoto

Takanori Hiramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Layout method and method of manufacturing semiconductor device
    Patent number: 9021405
    Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takanori Hiramoto, Toshio Hino, Tsuyoshi Sakata, Yutaka Mizuno, Katsuya Ogata
  • LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20120329266
    Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 27, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takanori Hiramoto, Toshio Hino, Tsuyoshi Sakata, Yutaka Mizuno, Katsuya Ogata