Patents by Inventor Takanori Hirota
Takanori Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10097189Abstract: A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.Type: GrantFiled: April 24, 2017Date of Patent: October 9, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takeshi Oshita, Takanori Hirota, Masato Suzuki
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Publication number: 20170230051Abstract: A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Takeshi OSHITA, Takanori HIROTA, Masato SUZUKI
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Patent number: 9666265Abstract: A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.Type: GrantFiled: December 11, 2015Date of Patent: May 30, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takeshi Oshita, Takanori Hirota, Masato Suzuki
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Publication number: 20160173108Abstract: A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.Type: ApplicationFiled: December 11, 2015Publication date: June 16, 2016Inventors: Takeshi OSHITA, Takanori HIROTA, Masato SUZUKI
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Patent number: 8624683Abstract: A semiconductor device is provided which can reduce a parasitic inductor and/or parasitic capacitance added to the wiring that couples spiral inductors and MOS varactors included in a VCO. An LC-tank VCO includes first and second spiral inductors, and first and second MOS varactors. As seen perpendicularly to the semiconductor substrate, the first and second MOS varactors are arranged in a region between the first spiral inductor and the second spiral inductor.Type: GrantFiled: May 11, 2011Date of Patent: January 7, 2014Assignee: Renesas Electronics CorporationInventor: Takanori Hirota
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Patent number: 8175205Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.Type: GrantFiled: September 16, 2010Date of Patent: May 8, 2012Assignee: Renesas Electronics CorporationInventors: Masashi Ishii, Takanori Hirota, Atsuhiko Ishibashi, Yasushi Hayakawa, Takeshi Oshita, Yoshiyuki Ota
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Publication number: 20110279186Abstract: A semiconductor device is provided which can reduce a parasitic inductor and/or parasitic capacitance added to the wiring that couples spiral inductors and MOS varactors included in a VCO. An LC-tank VCO includes first and second spiral inductors, and first and second MOS varactors. As seen perpendicularly to the semiconductor substrate, the first and second MOS varactors are arranged in a region between the first spiral inductor and the second spiral inductor.Type: ApplicationFiled: May 11, 2011Publication date: November 17, 2011Inventor: Takanori HIROTA
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Publication number: 20110007855Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.Type: ApplicationFiled: September 16, 2010Publication date: January 13, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masashi Ishii, Takanori Hirota, Atsuhiko Ishibashi, Yasushi Hayakawa, Takeshi Oshita, Yoshiyuki Ota
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Patent number: 7822158Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.Type: GrantFiled: June 30, 2006Date of Patent: October 26, 2010Assignee: Renesas Electronics CorporationInventors: Masashi Ishii, Takanori Hirota, Atsuhiko Ishibashi, Yasushi Hayakawa, Takeshi Oshita, Yoshiyuki Ota
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Publication number: 20070018704Abstract: PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.Type: ApplicationFiled: June 30, 2006Publication date: January 25, 2007Applicant: Renesas Technology Corp.Inventors: Masashi Ishii, Takanori Hirota, Atsuhiko Ishibashi, Yasushi Hayakawa, Takeshi Oshita, Yoshiyuki Ota
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Patent number: 6861883Abstract: Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta?Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta?Td?Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.Type: GrantFiled: February 10, 2003Date of Patent: March 1, 2005Assignee: Renesas Technology Corp.Inventors: Takanori Hirota, Atsuhiko Ishibashi
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Publication number: 20040027157Abstract: Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta−Td−Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.Type: ApplicationFiled: February 10, 2003Publication date: February 12, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takanori Hirota, Atsuhiko Ishibashi
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Patent number: 6084255Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption.Type: GrantFiled: July 30, 1998Date of Patent: July 4, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kimio Ueda, Takanori Hirota, Yoshiki Wada, Koichiro Mashiko
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Patent number: 5945843Abstract: A level conversion circuit as a semiconductor integrated circuit has a first load resistance (R1), a second load resistance (R2), a first NMOS transistor (MN3) and a second NMOS transistor (MN4) connected to them (R1 and R2) in parallel, respectively, that are driven directly by positive CMOS level signals, a first bipolar transistor (Q1), and a second bipolar transistor (Q2). Both emitters of the first and second bipolar transistors (Q1 and Q2) are connected commonly, and a voltage potential that is lower than a voltage potential of a collector of the first bipolar transistor (Q1) by a predetermined voltage potential is supplied into a base of the second bipolar transistor (Q2).Type: GrantFiled: October 24, 1997Date of Patent: August 31, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takanori Hirota, Yasushi Hayakawa