Abstract: A heat treatment system may include a heat treatment furnace; a supply device; a stack device configured to stack saggars in an up-down direction; a first conveyor configured to convey the saggars to the heat treatment furnace; an unstack device configured to unstack the stacked saggars; a recovery device; and a second conveyor configured to convey the saggars from the heat treatment furnace to the unstack device. At least one of the recovery device and the supply device may include at least a first conveyor mechanism and a second conveyor mechanism. The recovery device may further include a first recovery unit disposed on the first conveying path and a second recovery unit disposed on the second conveying path, or the supply device may further include a first supply unit disposed on the first conveying path and a second supply unit disposed on the second conveying path.

Abstract: A heat treatment system may include a heat treatment furnace configured to heat treat a material in a saggar; a conveyor configured to convey the saggar from an exit to an entrance of the heat treatment furnace; a recovery device configured to recover the material heat-treated; a supply device configured to supply a non-heat-treated material to the saggar; and a hood covering the conveying path. The conveying path may include a first conveying path disposed on at least a part of the conveying path between the recovery device and the supply device; and a second conveying path disposed on other part of the conveying path than the part where the first conveying path is disposed. The hood may be disposed over the second conveying path and may not be disposed over the first conveying path.

Abstract: A heat treatment system may include a heat treatment furnace configured to heat treat a material in a saggar; a conveyor configured to convey the saggar from an exit to an entrance of the heat treatment furnace; a recovery apparatus configured to recover the material heat-treated from the saggar; and a supply device configured to supply a non-heat treated material to the saggar. The conveyor may include a conveyor mechanism and a drive unit configured to drive the conveyor mechanism. The recovery apparatus may comprise a recovery unit disposed at a position where the conveyor mechanism is not disposed and configured to recover the material in the saggar; a transport device configured to transport the saggar between a placement position on the conveyor mechanism and a recovery position above the recovery unit; and an inversion mechanism configured to invert the saggar at the recovery position.

Abstract: A heat treatment system may include a heat treatment furnace configured to heat treat a material in a saggar, the saggar including a saggar body and a lid; a lid removing device configured to remove the lid from the saggar; a body conveyor configured to convey the saggar body; a lid conveyor configured to convey the lid; a recovery device configured to recover the material from the saggar body; a supply device configured to supply a non-heat-treated material to the saggar body; and a lid attaching device configured to attach the lid to the saggar body. A conveying time for the lid to be conveyed from an entrance to an exit of a conveying path of the lid conveyor may be shorter than a conveying time for the saggar body to be conveyed from an entrance to an exit of a conveying path of the body conveyor.

Abstract: A heat treatment furnace disclosed herein may include: a heat treatment unit configured to heat-treat an object; a cooling unit configured to cool the object heat-treated by the heat treatment unit; and a conveyor configured to convey the object in the heat treatment unit and the cooling unit. The cooling unit may include a housing, wherein the housing is disposed below a conveyance path on which the object is conveyed by the conveyor and configured to cool the object being conveyed by the conveyor by liquid flowing inside the housing. The housing may include an upper plate facing the object being conveyed by the conveyor. The upper plate may be tilted so that gas stays at a predetermined portion of the housing while the liquid is flowing in the housing.

Abstract: This invention may be applied for performing a burst write of write data, and increases efficiency of data transfer to memory. A buffer memory device transfers data between processors and a main memory in response to a memory access request issued by each of the processors. The buffer memory device includes: buffer memories each of which holds write data corresponding to the write request issued by a corresponding processor; a memory access information obtaining unit which obtains memory access information indicating a type of the memory access request; a determining unit which determines whether or not the type indicated by the memory access information obtained by the memory access information obtaining unit meets a predetermined condition; and a control unit which drains, to the main memory, data held in one of the buffer memories which meets the predetermined condition, when determined that the predetermined condition is met.

Abstract: A cache memory according to the present invention includes: a first port for input of a command from the processor; a second port for input of a command from a master other than the processor; a hit determining unit which, when a command is input to said first port or said second port, determines whether or not data corresponding to an address specified by the command is stored in said cache memory; and a first control unit which performs a process for maintaining coherency of the data stored in the cache memory and corresponding to the address specified by the command and data stored in the main memory, and outputs the input command to the main memory as a command output from the master, when the command is input to the second port and said hit determining unit determines that the data is stored in said cache memory.

Abstract: A cache memory according to an aspect of the present invention including entries each of which includes a tag address, line data, and a dirty flag, the cache memory includes: a command execution unit which rewrites, when a first command is instructed by a processor, a tag address included in at least one entry specified by the processor among the entries to a tag address corresponding to an address specified by the processor, and to set a dirty flag corresponding to the entry; and a write-back unit which writes, back to a main memory, the line data included in the entry in which the dirty flag is set.

Abstract: Memory access is accelerated by performing a burst read without any problems caused due to rewriting of data. A buffer memory device reads, in response to a read request from a processor, data from a main memory including cacheable and uncacheable areas. The buffer memory device includes an attribute obtaining unit which obtains the attribute of the area indicated by a read address included in the read request; an attribute determining unit which determines whether or not the attribute obtained by the attribute obtaining unit is burst-transferable; a data reading unit which performs a burst read of data including data held in the area indicated by the read address, when determined that the attribute obtained by the attribute obtaining unit is burst-transferable; and a buffer memory which holds the data burst read by the data reading unit.

Abstract: A pseudo-physical address is used for accessing a memory from a CPU (Central Processing Unit). One of function blocks that is needed for the current application program is selected based on the pseudo-physical address, and the pseudo-physical address is translated to a real physical address by the selected function block. There are provided parallel lines of memory access functions extending from the CPU, whereby it is possible to perform an optimal memory access transaction for each application program, and it is possible to improve the memory access performance without lowering the operation frequency and without increasing the number of cycles required for a memory access.

Abstract: In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to deal with the case in which a set-up time in the register is not satisfied due to an increase of the delay time, and the delay time of the clock signal is changed in response to the change of the delay time of the circuit in respective modes. Thereby, the set-up time of data in the register can be satisfied, and an operation frequency of the circuit can be prevented from lowering.

Abstract: A register circuit includes a passage control circuit and a holding circuit. The passage control circuit includes a first transistor having a gate to which a clock signal is input, a second transistor having a gate to which a data signal is input, and a third transistor having a gate to which a control signal is input, with source-drain paths of the first, second, and third transistors being connected in series. The passage control circuit enables passage of the data signal to the holding circuit according to a state of the clock signal when the control signal is in one of an active state and an inactive state, and disables passage of the data signal to the holding circuit when the control signal is in the other one of the active state and the inactive state. The holding circuit latches the data signal passed from the passage control circuit.

Abstract: A semiconductor device includes a cell source line which supplies a voltage to logic circuits, a capacity source line which supplies a voltage to the cell source line, a control circuit source line, switches by which the cell source line is isolated from or connected to the capacity source line and the control circuit source line, and buffer circuits which drive signals which control the switches, respectively. When the system is activated, a potential is applied to the capacity source line for charging, after which the cell-to-capacity switch is turned on. Then, a voltage is applied to the cell source line, which allows a steep rise in voltage at the cell source line. As a result, charging time is reduced and flow-through current which flows through transistors constituting the logic circuit can be reduced as well.

Abstract: A register circuit includes a passage control circuit and a holding circuit. The passage control circuit includes a first transistor having a gate to which a clock signal is input, a second transistor having a gate to which a data signal is input, and a third transistor having a gate to which a control signal is input, with source-drain paths of the first, second, and third transistors being connected in series. The passage control circuit enables passage of the data signal to the holding circuit according to a state of the clock signal when the control signal is in one of an active state and an inactive state, and disables passage of the data signal to the holding circuit when the control signal is in the other one of the active state and the inactive state. The holding circuit latches the data signal passed from the passage control circuit.

Abstract: In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to deal with the case in which a set-up time in the register is not satisfied due to an increase of the delay time, and the delay time of the clock signal is changed in response to the change of the delay time of the circuit in respective modes. Thereby, the set-up time of data in the register can be satisfied, and an operation frequency of the circuit can be prevented from lowering.

Abstract: A semiconductor device that achieves high speed and low power consumption that can be used in a real-time system by preventing held data from disappearing at the time of power shutdown and sharply rising power while also preventing a through-current at the time of power resumption. During normal operation, the switch is on, and the clock generating circuit and the data holding circuit are operated with the first power supply voltage. When data holding is required at the time of power shutdown, the switch and the first power supply voltage supplied to the logic circuit are turned off, and the clock generating circuit and the data holding circuit are operated with the second power supply voltage.

Abstract: A semiconductor device is provided which includes a cell source line 102 which supply a voltage to logic circuits 101, a capacity source line 103 which supplies a voltage to the cell source line 102, a control circuit source line 107, switches 104 and 108 by which the cell source line 102 is isolated from or connected to the capacity source line 103 and the control circuit source line 107, and buffer circuits 106 and 110 which drive signals 105 and 109 which control the switches 104 and 108, respectively. When the system is activated, a potential is applied to the capacity source line 103 for charging, after which the cell-to-capacity switch 104 is turned on. Then a voltage is applied to the cell source line 102, which allows a steep rise in voltage at the cell source line 102. As a result, charging time is reduced and flow-through current which flows through transistors comprising the logic circuit 101 can be reduced as well.

Abstract: The present invention provides a semiconductor device that achieves high speed and low power consumption and can be used in a real-time system by preventing the held data from disappearing at the time of power shutdown and turning power on sharply while preventing a through-current at the time of power resumption. During normal operation, the switch is on, and the clock generating circuit and the data holding circuit are operated with the first power supply voltage, and when data holding is required at the time of power shutdown, the switch is turned off, and the clock generating circuit and the data holding circuit are operated with the second power supply voltage, and the first power supply voltage supplied to the logic circuit is shut down.