Abstract: A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor in a memory cell, and small-area vertical transistors each including a channel formation region on a side surface of an opening portion provided in an insulating layer are used as the two transistors. The memory cell includes a conductor having a function of a gate electrode of the first transistor and a function of one of a source electrode and a drain electrode of the second transistor. The memory cells are placed in a staggered arrangement, so that the memory device can be highly integrated.

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first substrate provided with a first peripheral circuit having a function of driving a first memory cell and a first memory cell layer including a second substrate and a first element layer including the first memory cell. The first memory cell includes a first transistor and a first capacitor. The first transistor includes a semiconductor layer including a metal oxide in its channel formation region. The first memory cell layer is provided to be stacked over the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate. The second substrate includes a circuit for performing writing of data to or reading of data from the first memory cell. The first peripheral circuit and the first memory cell are electrically connected to each other through a first through electrode provided in the second substrate and the first element layer.

Abstract: A semiconductor device capable of detecting a micro-short circuit of a secondary battery is provided. The semiconductor device includes a first source follower, a second source follower, a transistor, a capacitor, and a comparator. A negative electrode potential and a positive electrode potential of the secondary battery are supplied to the semiconductor device, a first potential is input to the first source follower, and a second potential is input to the second source follower. A signal for controlling the conduction state of the transistor is input to a gate of the transistor, and an output potential of the first source follower related to the potential between the positive electrode and the negative electrode of the secondary battery is sampled.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor, a capacitor, and a first insulating layer. The first insulating layer is provided over a first conductive layer and a second conductive layer and includes a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. The transistor is a vertical transistor in which a channel formation region is provided along the side wall of the first opening. The capacitor is a vertical capacitor in which a pair of electrodes and a dielectric are provided along the side surface of the second opening.

Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided. The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

Abstract: A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings.

Abstract: A battery protection circuit with a novel configuration and a power storage device including the battery protection circuit are provided. The battery protection circuit includes a switch circuit for controlling charge and discharge of a battery cell; the switch circuit includes a mechanical relay, a first transistor, and a second transistor; the switch circuit has a function of controlling electrical connection between a first terminal and a second terminal; the mechanical relay has a function of breaking electrical connection between the first terminal and the second terminal; the first transistor has a function of supplying first current between the first terminal and the second terminal; the second transistor has a function of supplying second current between the first terminal and the second terminal; and the first current is higher than the second current.

Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a memory cell including a first ferroelectric capacitor and a reference memory cell including a second ferroelectric capacitor. In a first period, first binary data is written to the memory cell, and first reference binary data is written to the reference memory cell. In a second period, the first binary data is read from the memory cell, and the first reference binary data is read from the reference memory cell. In a third period, logic operation of the first binary data and the first reference binary data is performed. In a fourth period, second binary data is written to the memory cell, and second reference binary data is written to the reference memory cell. A value of the first binary data and a value of the second binary data are different from each other, and a value of the first reference binary data and a value of the second reference binary data are different from each other.

Abstract: A highly reliable memory device is provided. The memory device includes a memory control unit that includes an input/output unit, a control unit, and a first management unit and a memory unit that includes a plurality of memory blocks. The first management unit includes a plurality of first memory elements, the control unit has a function of converting an address input through the input/output unit to an address of the memory block corresponding to the address, with use of a first management table retained in the plurality of first memory elements, and the first memory elements each include a ferroelectric. The control portion may include a function of not using a defective memory cell and may have a function of performing error correction of readout data.

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a memory cell including a transistor and a capacitor that includes a ferroelectric; a word line; a bit line; and a plate line. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor. The other electrode of the capacitor is electrically connected to the plate line. The semiconductor device has a function of supplying a potential that controls an on state or an off state of the transistor to the word line, a function of supplying a first potential or a second potential to the bit line, and a function of supplying a third potential, a fourth potential, or a fifth potential to the plate line.

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data to the digital calculator as digital data. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data to the analog calculator as analog data. The analog calculator has a function of performing product-sum operation using the second weight data.

Abstract: A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

Abstract: To provide a novel semiconductor device.

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory elements each provided with a writing transistor and a reading transistor. An oxide semiconductor is used in a semiconductor layer of the writing transistor, whereby a storage capacitor is not necessary or the size of the storage capacitor can be reduced. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory element is read out.