Abstract: A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

Abstract: A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

Abstract: An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.

Abstract: An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.

Abstract: In a phased array antenna that has a configuration in which a plurality of antenna panels, in each of which a plurality of antenna elements are arrayed, are connected in the form of a plane and that radiates power transmission microwaves in the arrival direction of a pilot signal sent from an electric-power receiving facility (rectenna system), by controlling the phases of signals input to and output from the antenna elements. An arithmetic processing section, which is provided in each of the antenna panels, calculates the phase shifts of power transmission microwaves to be radiated from the antenna elements. Then, the phase information indicating the phase shifts calculated by the arithmetic processing section is sent to at least three adjacent antenna panels by a transmission and reception section provided in each of the antenna panels.

Abstract: In a phased array antenna that has a configuration in which a plurality of antenna panels, in each of which a plurality of antenna elements are arrayed, are connected in the form of a plane and that radiates power transmission microwaves in the arrival direction of a pilot signal sent from an electric-power receiving facility (rectenna system), by controlling the phases of signals input to and output from the antenna elements. An arithmetic processing section, which is provided in each of the antenna panels, calculates the phase shifts of power transmission microwaves to be radiated from the antenna elements. Then, the phase information indicating the phase shifts calculated by the arithmetic processing section is sent to at least three adjacent antenna panels by a transmission and reception section provided in each of the antenna panels.