Patents by Inventor Takanori Ozawa

Takanori Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5563081
    Abstract: A method for making a nonvolatile memory device having a field effect transistor for storing information, and a Schottky diode in series with the field effect transistor. The field effect transistor includes source and drain regions in a semiconductor substrate, with a channel region interposed between them and a gate electrode above the channel region. A ferroelectric gate film is sandwiched between the channel region and the gate electrode. In the method, a conductive barrier meterial is deposited in contact with the source region of the field effect transistor to make the Schottky diode. In reading information from the memory device, voltage is applied to a serial circuit consisting of the field effect transistor and the Schottky diode to turn the Schottky diode on.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: October 8, 1996
    Assignee: Rohm Co., Inc.
    Inventor: Takanori Ozawa
  • Patent number: 5498888
    Abstract: A semiconductor device having a source region, a drain region, a channel region between the source region and the drain region, a gate consisting of at least three input electrodes provided above the channel region, and a potential modulating film provided between the channel region and the gate. The potential modulating film can assume at least two potential modulating states, so that the potential of the channel region is modulated between and held at different values. The potential of the channel region is modulated by changing the state of the potential modulating film. Specifically, the potential of the channel region is modulated by not only applying voltages to the input electrodes but also controlling the state of the potential modulating film.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: March 12, 1996
    Assignee: Rohm Co., Ltd.
    Inventor: Takanori Ozawa
  • Patent number: 5477068
    Abstract: A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.
    Type: Grant
    Filed: March 17, 1993
    Date of Patent: December 19, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Takanori Ozawa
  • Patent number: 5461249
    Abstract: A drain diffusion layer acting as a drain of both of a memory transistor and a selection transistor, and a source diffusion layer acting as a source of both of the memory transistor and the selection transistor are formed in a semiconductor substrate. A floating gate having a convex upper surface is formed on a tunnel insulating film in the vicinity of the drain diffusion layer. A common gate acting both as a control gate of the memory transistor and as a gate of the selection transistor is formed such that its one end is located over the floating gate and the other end is located in the vicinity of the source diffusion layer.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: October 24, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Takanori Ozawa
  • Patent number: 5402374
    Abstract: In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: March 28, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Masataka Tsuruta, Noriyuki Shimoji, Hironobu Nakao, Takanori Ozawa
  • Patent number: 5361225
    Abstract: A nonvolatile memory device having a field effect transistor for storing, which includes source and drain regions in a semiconductor substrate with a channel region interposed between them and a gate electrode above the channel region with a ferroelectric gate film sandwiched between them. Barrier metal is formed in contact with the source region of the field effect transistor for storing to make a Schottky diode in serial connection with the field effect transistor for storing. In reading information, voltage is applied to a serial circuit consisting of the field effect transistor for storing and the Schottky diode to turn the Schottky diode on.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: November 1, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Takanori Ozawa
  • Patent number: 5332915
    Abstract: A high dielectric film instead of an oxidizing film conventionally used is used in the non-volatile memory of an MoNoS construction. Using a mixed film composed of a high dielectric constant film and an amorphous insulating film for the trap film, the ratio of the voltage applied to the tunnel oxidizing film is increased so that writing and erasing operations can be effected with a low voltage. Penetration of the electrons into the electrode and the flow of positive holes from the electrode are prevented so as to increase the flow efficiency.
    Type: Grant
    Filed: October 21, 1992
    Date of Patent: July 26, 1994
    Assignee: Rohm Co., Ltd.
    Inventors: Noriyuki Shimoji, Takanori Ozawa, Hironobu Nakao
  • Patent number: 5319229
    Abstract: A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: June 7, 1994
    Inventors: Noriyuki Shimoji, Takanori Ozawa, Hironobu Nakao
  • Patent number: 5286994
    Abstract: A trap film assembly of a semiconductor memory device includes a tunnel oxide layer formed on a semiconductor substrate and plural multi-layer film layers laminated on the tunnel oxide film. A thickness of each multi-layer film layer is sequentially increased in a direction away from the semiconductor substrate and towards a gate electrode, thereby displacing the charge centroid of the assembly towards the semiconductor substrate.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: February 15, 1994
    Assignee: Rohm Co., Ltd.
    Inventors: Takanori Ozawa, Noriyuki Shimoji