Patents by Inventor Takanori Seino

Takanori Seino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5406142
    Abstract: When the input signal IN1 changes from a ground voltage GND to a first voltage -E1 and from the first voltage -E1 to the ground voltage GND, the output potential of the -E2 system flip-flop circuit changes gradually. The inverted signal from the -E1 system inverter circuit is supplied to the -E2 system inverter circuit earlier than the output signal (high-potential signal) of the -E2 system flip-flop circuit. This eliminates a period of time when all the MOSFETs in the -E2 system inverter circuit turn on simultaneously, thereby reducing a through current in the -E2 system inverter circuit. Consequently, the circuit operation can be stabilized by decreasing through currents flowing in the -E1 system inverter circuit and the -E2 system inverter circuit using the output signal of the -E2 system flip-flop circuit as an input.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: April 11, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Nakama, Hiroshi Yoshida, Takanori Seino