Abstract: A communication plate in which are provided a first communication channel communicating with the first pressure chamber and the second pressure chamber and a first common liquid chamber communicating with the first pressure chamber and the second pressure chamber at positions different from positions at which the first communication channel communicates with the first pressure chamber and the second pressure chamber, and a nozzle substrate in which a first nozzle communicating with the first pressure chamber and the second pressure chamber in common via the first communication channel is provided. A second communication channel communicating with the first common liquid chamber and communicating with the first pressure chamber and the second pressure chamber in common is provided in the pressure chamber substrate or the communication plate.

Abstract: A wireless repeater holds control information for controlling a communication status of a first wireless communication path for short-range wireless communication and authentication data required to permit short-range wireless communication, automatically permits connection when receiving a connection request using the first wireless communication path from the mobile terminal, determines, when receiving an authentication request with authentication data requesting a start of wireless communication from the connected mobile terminal, whether to authenticate the authentication-request-source mobile terminal, based on a result of comparing the authentication data attached to the authentication request from the mobile terminal with the authentication data held in the wireless repeater, and sets, when the mobile terminal is authenticated, a status of the wireless repeater to a status for performing wireless communication with the mobile terminal using the first wireless communication path.

Abstract: An image signal processor apparatus according to an embodiment is provided with a first image signal processor apparatus configured to receive first image data as input and a second image signal processor apparatus configured to receive second image data as input, in which the second image signal processor apparatus, using a first signal that the first image signal processor apparatus uses for first image processing to adjust pixel values of the first image data, performs the first image processing to adjust pixel values of the second image data.

Abstract: An image signal processor apparatus according to an embodiment is provided with a first image signal processor apparatus configured to receive first image data as input and a second image signal processor apparatus configured to receive second image data as input, in which the second image signal processor apparatus, using a first signal that the first image signal processor apparatus uses for first image processing to adjust pixel values of the first image data, performs the first image processing to adjust pixel values of the second image data.

Abstract: A microprocessor includes a first ringed shift register having a plurality of registers storing a plurality of context information respectively, the registers being connected in a loop, an instruction decoder transmitting the context information to a reference register in the first ringed shift register, an instruction execution unit exchanging the context information with the reference register, and a control unit controlling the first ringed shift register to perform a shift operation to carry out context switching.

Abstract: A pipeline processor including an instruction decode unit configured to decode fetched instruction, and to selectively issue one of a user customizable instruction defined by a user and a core instruction. A core instruction execution unit is configured to execute the issued core instruction. A user customizable instruction unit is configured to execute the issued user customizable instruction. A reorder buffer is configured to temporarily store instruction execution results of the core instruction execution unit and the user customizable instruction unit, and to reorder the instruction execution results in accordance with an order in which the core instruction and the user customizable instruction were issued.

Abstract: The microprocessor is simply structured, shortening the time for design and verification, and protecting tasks while executing multiple tasks The microprocessor includes an instruction fetch unit having a request queue configured to issue, to a bus interface unit, a bus request due to an instruction fetch and retain, of instruction fetch requests output to the bus interface unit, unprocessed requests. The microprocessor also includes a load/store unit configured to issue a bus request emanating from a load or a store instruction to the bus interface unit; a decode unit configured to decode an instruction from the instruction fetch unit; an execution unit configured to execute an instruction from the decode unit; and an OR gate configured to make an output signal active and output it to the instruction fetch unit when any one of signals from the decode unit, the execution unit, and the load/store unit becomes active.

Abstract: A preprocessor processes a first circuit description file containing a first hardware description language and a second hardware description language on the basis of a preprocessor control file. The preprocessor converts at least a portion described by the first hardware description language in the first circuit description file into the second hardware description language to create and output a second circuit description file.

Abstract: A microprocessor includes a first ringed shift register having a plurality of registers storing a plurality of context information respectively, the registers being connected in a loop, an instruction decoder transmitting the context information to a reference register in the first ringed shift register, an instruction execution unit exchanging the context information with the reference register, and a control unit controlling the first ringed shift register to perform a shift operation to carry out context switching.

Abstract: A preprocessor processes a first circuit description file containing a first hardware description language and a second hardware description language on the basis of a preprocessor control file. The preprocessor converts at least a portion described by the first hardware description language in the first circuit description file into the second hardware description language to create and output a second circuit description file.