Abstract: A data line driver includes a counter, a data converter, a gray-scale voltage generating circuit, multiple voltage selectors and multiple output circuits. Each voltage selector receives n voltages generated by the gray-scale voltage generating circuit. The voltage selector includes: n switches; a capacitor which holds electric charges; and a selector which generates n control signals to control ON and OFF of the n switches, respectively. The voltage selector selects two voltages out of the n voltages, and makes a control signal variable which is inputted into one of switches to which the two voltages are respectively applied. Thereby, the voltage selector generates k intermediate voltages, and outputs the n voltages and the k intermediate voltages.

Abstract: Output circuits OC1-OC240 supplied with picture signals VIN to output drive signals are provided. Each of the output circuits OC includes a switching element SW1, a capacitor C1 and a switching element SW2 provided at a first path, and a switching element SW3, a capacitor C2 and a switching element SW4 provided at a second path connected in parallel with the first path, and includes a sample-hold circuit SH1 supplied with a picture signal and a hold switching signal of which level is switched at a first period to alternately store the picture signal into the capacitor C1 or the capacitor C2 in accordance with hold switching signal to output it, and an amplifier AMP1 supplied with an output of this circuit SH1 to amplify that output to output it as a drive signal. Further, buffers are provided every output circuits OC. These buffers are connected to each other in series. Hold switching signal inputted from the external is inputted to the buffers and are propagated therethrough.

Abstract: In a level shift circuit having a bias circuit and an output circuit, the current consumption of the bias circuit can be suppressed, and further the delay of the output signal relative to the input signal can be reduced. The ratio circuit comprises a bias circuit block (5) composed of a transistor (1) connected to a high potential power source (7) and having a gate to which an input bias INBIAS is applied through a bias input terminal (11), a transistor (2) connected in series to the transistor (1) so as to function as a resistance, and a transistor (13) connected in series to the transistor (2) and a low potential power source (8); and an output circuit block (6) composed of a transistor (3) connected to the high potential power source (7) and having a gate to which an input signal IN is applied through an input terminal (10) and a drain from which an output signal OUT is derived to an output terminal (12), and a transistor (4) connected in series to the transistor (3) and a low potential power source (8).