Patents by Inventor Takanori Yamashita

Takanori Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170323848
    Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.
    Type: Application
    Filed: July 27, 2017
    Publication date: November 9, 2017
    Inventors: Takanori Yamashita, Toshinori Kiyohara
  • Patent number: 9754865
    Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.
    Type: Grant
    Filed: June 15, 2014
    Date of Patent: September 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takanori Yamashita, Toshinori Kiyohara
  • Patent number: 9749570
    Abstract: Provided is an imaging apparatus, including: a driving circuit switching between a current supplying state and a current non-supplying state of the current sources included in column circuits in the respective columns; at least one second readout line to which image signals output from the column circuits in the respective columns are input; switches each having one terminal and another terminal; and a switch control circuit configured to output switch control signals for respectively controlling the switches to be turned on or off, each of the one terminals being connected to corresponding second readout line and each of the another terminals being connected commonly to an output line, in which, in a period in which the switch control signals for respectively controlling the switches to be turned on are output, the number of the current sources controlled to be in the current supplying state by the driving circuit is constant.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 29, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Yamashita, Yoshikazu Yamazaki
  • Patent number: 9698189
    Abstract: The disclosure provides at least a photoelectric converter, and at least a photoelectric conversion system, including a plurality of pixels each having a photoelectric conversion layer and a pixel electrode; a first electrode that supplies a potential to each of the photoelectric conversion layers of a plurality of pixels in common, and a second electrode that supplies the potential to the first electrode. The pixel electrode is formed by metal and further includes an oxide conductive film disposed between the first electrode and the second electrode.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 4, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takanori Yamashita
  • Patent number: 9653498
    Abstract: An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 16, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Yamashita, Seiji Hashimoto
  • Patent number: 9635300
    Abstract: An absolute value between a reset voltage to reset a signal line and a first voltage supplied from a signal source is smaller than an absolute value between the reset voltage and a second voltage supplied from the signal source.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 25, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Yamashita, Yoshikazu Yamazaki
  • Patent number: 9537120
    Abstract: A polymer battery module packaging sheet includes, as essential components, a base layer (61), an aluminum layer (62), chemical conversion coatings (64a, 64b) coating the opposite surfaces of the aluminum layer (62), and an innermost layer (63). The chemical conversion coatings (64a, 64b) are formed by processing the opposite surfaces of the aluminum layer (62) by a phosphate treatment method. The base layer (61) and the innermost layer (63) are bonded to the chemical conversion coatings (64a, 64b) of the aluminum layer (62) with adhesive layers (65a, 65b), respectively.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: January 3, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takanori Yamashita, Masataka Okushita, Kazuki Yamada, Rikiyama Yamashita, Hiroshi Miyama, Youichi Mochizuki
  • Patent number: 9502451
    Abstract: An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 22, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Yamashita, Seiji Hashimoto
  • Publication number: 20160323529
    Abstract: Provided is a signal readout circuit, including: an input unit to which a first signal and a second signal are input; a first holding capacitor configured to hold the first signal input from the input unit; a second holding capacitor configured to hold the second signal input from the input unit; and an amplifier circuit including an input terminal and an output terminal and configured to be able to input a signal held in one of the first holding capacitor and the second holding capacitor to the input terminal, in which, in a period in which the first signal is input from the input unit to the first holding capacitor, the first signal is input to the input terminal of the amplifier circuit via the first holding capacitor.
    Type: Application
    Filed: April 21, 2016
    Publication date: November 3, 2016
    Inventor: Takanori Yamashita
  • Publication number: 20160300878
    Abstract: An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 13, 2016
    Inventors: Takanori Yamashita, Seiji Hashimoto
  • Publication number: 20160071986
    Abstract: The disclosure provides at least a photoelectric converter, and at least a photoelectric conversion system, including a plurality of pixels each having a photoelectric conversion layer and a pixel electrode; a first electrode that supplies a potential to each of the photoelectric conversion layers of a plurality of pixels in common, and a second electrode that supplies the potential to the first electrode. The pixel electrode is formed by metal and further includes an oxide conductive film disposed between the first electrode and the second electrode.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 10, 2016
    Inventor: Takanori Yamashita
  • Publication number: 20160035772
    Abstract: An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member.
    Type: Application
    Filed: June 24, 2015
    Publication date: February 4, 2016
    Inventors: Takanori Yamashita, Seiji Hashimoto
  • Publication number: 20160006967
    Abstract: Provided is an imaging apparatus, including: a driving circuit switching between a current supplying state and a current non-supplying state of the current sources included in column circuits in the respective columns; at least one second readout line to which image signals output from the column circuits in the respective columns are input; switches each having one terminal and another terminal; and a switch control circuit configured to output switch control signals for respectively controlling the switches to be turned on or off, each of the one terminals being connected to corresponding second readout line and each of the another terminals being connected commonly to an output line, in which, in a period in which the switch control signals for respectively controlling the switches to be turned on are output, the number of the current sources controlled to be in the current supplying state by the driving circuit is constant.
    Type: Application
    Filed: June 22, 2015
    Publication date: January 7, 2016
    Inventors: Takanori Yamashita, Yoshikazu Yamazaki
  • Patent number: 9172837
    Abstract: Provided is a light source for exposure including: a circuit section which includes plural pixel circuits arranged in one direction, a scanning circuit which outputs a scanning signal, a scanning line which supplies the pixel circuits with the scanning signal; light-emitting elements connected to the pixel circuits; and data lines which supply a lead wire with a data signal via the pixel circuits, wherein a data line group including the plural data lines, a light-emitting element group including the plural light-emitting elements, and the circuit section are arranged in this order in a direction perpendicular to a direction in which the plural pixel circuits are arranged.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 27, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kouji Ikeda, Takanori Yamashita, Masami Iseki
  • Publication number: 20150304584
    Abstract: An absolute value between a reset voltage to reset a signal line and a first voltage supplied from a signal source is smaller than an absolute value between the reset voltage and a second voltage supplied from the signal source.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 22, 2015
    Inventors: Takanori Yamashita, Yoshikazu Yamazaki
  • Patent number: 9167635
    Abstract: A light emitting apparatus includes a light emitting element, a driving circuit which has a driving transistor having a gate, a drain, and a source, and a capacitor having one end connected to the gate, a power line, and first and second voltage lines, and, in a period in which the gate and the drain are short-circuited and the drain and the light emitting element are blocked, the source is connected to the first voltage line and the other end of the capacitor is connected to the second voltage line to hold a voltage in the capacitor, and, in a period in which the gate and the drain are disconnected and the drain and the light emitting element are connected, the source is connected to the power line, and the other end of the capacitor is connected to the source to supply a current to the light emitting element.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 20, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Yamashita, Masami Iseki, Tsuyoshi Yabukane
  • Patent number: 9165508
    Abstract: A display apparatus includes: a plurality of pixel circuits 6; a reference voltage source for supplying a reference voltage to a reference voltage line 4; a first switch for connecting the reference voltage source to the reference voltage line 4; a data line 5 for supplying a data voltage to the pixel circuit, wherein the pixel circuit 6 includes a light emitting element, a driving transistor M1 having a source connected to an anode of the light emitting element, a holding capacitor CS having one end connected to a gate of the driving transistor M1 and having the other end connected to the source of the driving transistor M1, a second switch for connecting the gate of the driving transistor M1 to the data line 5, and a third switch for connecting the source of the driving transistor M1 to the reference voltage line 4.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 20, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Yamashita, Masami Iseki, Tatsuhito Goden
  • Publication number: 20150260797
    Abstract: Disclosed is a method for manufacturing an electrochemical cell, wherein an insulation failure product can be accurately rejected, and an electrochemical cell can be used again after the insulation failure inspection. In the method for manufacturing the electrochemical cell (1), which is configured by hermetically housing an electrochemical cell main body (20) such that the leading end of a metal terminal (21) protrudes to the outside of the outer housing (10), an impulse voltage is applied between the metal terminal (21) and a metal foil layer (12), the waveform of the voltage applied to the capacitance between the metal terminal (21) and the metal foil layer (12) is measured, and the insulation failure inspection step is performed.
    Type: Application
    Filed: June 1, 2015
    Publication date: September 17, 2015
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takanori YAMASHITA, Hirohisa AKITA, Noboru AKIYAMA, Masataka OKUSHITA
  • Patent number: 9076601
    Abstract: A method for manufacturing an electrochemical cell includes housing a main cell body in an outer packaging body of packaging material formed by laminating a metal foil layer and a heat-sealable resin layer, provided the tip ends of a first metal terminal and a second metal terminal are protruding outside the outer packaging body, heat-sealing a peripheral edge portion of the outer packaging body so the outer packaging body has the first and second terminals protruding; applying a voltage between the first terminal and the foil layer or between the second terminal and the foil layer; and inspecting for insulation failure from a short circuit between the first or second terminal and the foil layer or from a crack in the heat-sealable resin layer, based on a variation of a voltage held between the one of the metal terminals and the metal foil layer after halting the voltage.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 7, 2015
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takanori Yamashita, Hirohisa Akita, Noboru Akiyama, Masataka Okushita
  • Patent number: 9036211
    Abstract: A light emitting apparatus including: a plurality of light emitting elements; a drive circuit including a transistor and a capacitor having one end connected to a gate of the transistor; and a signal supply circuit for receiving a digital gradation signal and outputting an analog voltage signal to the drive circuit, including a computation circuit configured to correct the input digital gradation signal to generate a corrected digital gradation signal, in which the drive circuit is configured to conduct an auto-zero operation which reduce the gate-source voltage of the transistor to a threshold voltage by flowing the drain current to the capacitor, and the computation circuit is configured to generate the corrected digital gradation signal by multiplying a correction coefficient to the input digital gradation signal subtracted by a particular signal common to the plurality of light emitting elements.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 19, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Yamashita, Masami Iseki, Kouji Ikeda, Shuhei Takahashi