Patents by Inventor Takao Adachi

Takao Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183484
    Abstract: The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 23, 2021
    Assignee: ULTRAMEMORY INC.
    Inventors: Fumitake Okutsu, Takao Adachi
  • Publication number: 20210143129
    Abstract: The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventors: Fumitake OKUTSU, Takao ADACHI
  • Publication number: 20210018952
    Abstract: Provided is a semiconductor module which enables a memory bandwidth to be widened, and which enables data transfer efficiency to be improved by reducing power consumption. A semiconductor module 1 comprises: an interposer 10; and a processing unit 20 which has a plurality of processing unit main bodies 21 arrayed to be side by side with each other in a first direction F1 along the plate surface of the interposer 10, and which is placed on the interposer 10 so as to be electrically connected to the interposer 10. The processing unit main bodies 21 are provided with a plurality of subset units 22 each including: one arithmetic unit 23 including at least one core 25; and one memory unit 24 that is configured from a stacked-type RAM module and that is disposed to be side by side with the calculation unit 23 in the first direction F1. The plurality of subset units 22 are arrayed to be side by side with each other in a second direction F2 that intersects with the first direction F1.
    Type: Application
    Filed: June 2, 2017
    Publication date: January 21, 2021
    Inventors: Kazuhiko KAJIGAYA, Takao ADACHI
  • Publication number: 20200328184
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Ryuji TAKISHITA, Takao ADACHI
  • Patent number: 10741525
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 11, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Ryuji Takishita, Takao Adachi
  • Patent number: 10714151
    Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 14, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
  • Publication number: 20200135696
    Abstract: The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.
    Type: Application
    Filed: June 2, 2017
    Publication date: April 30, 2020
    Inventors: Ryuji TAKISHITA, Takao ADACHI
  • Patent number: 10615850
    Abstract: The objective of the invention is to provide technology allowing data taking a plurality of values to be transmitted and received using one set of coils when sending data through TCI technology using magnetic field coupling. This layered semiconductor device has at least a first semiconductor chip and a second semiconductor chip layered therein, the first semiconductor chip transmitting data in a contactless manner, and the second semiconductor chip receiving, in a contactless manner, the data that has been transmitted. The first semiconductor chip contains: a transmission unit outputting a transmission signal that may acquire, on the basis of the value of the data to be sent, at least 3 types of states representing the value of the data; and a transmission coil converting the transmission signal into a magnetic field signal.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 7, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yuji Motoyama, Takao Adachi
  • Publication number: 20200090708
    Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Yasutoshi YAMADA, Kouji UEMURA, Takao ADACHI
  • Patent number: 10529385
    Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 7, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
  • Publication number: 20190349029
    Abstract: The objective of the invention is to provide technology allowing data taking a plurality of values to be transmitted and received using one set of coils when sending data through TCI technology using magnetic field coupling. This layered semiconductor device has at least a first semiconductor chip and a second semiconductor chip layered therein, the first semiconductor chip transmitting data in a contactless manner, and the second semiconductor chip receiving, in a contactless manner, the data that has been transmitted. The first semiconductor chip contains: a transmission unit outputting a transmission signal that may acquire, on the basis of the value of the data to be sent, at least 3 types of states representing the value of the data; and a transmission coil converting the transmission signal into a magnetic field signal.
    Type: Application
    Filed: February 18, 2016
    Publication date: November 14, 2019
    Inventors: Yuji MOTOYAMA, Takao ADACHI
  • Publication number: 20190303099
    Abstract: A sound collection apparatus and a sound collection method for accurately collecting a target sound are provided. A sound collection apparatus (1) collects an acoustic signal, and comprises: a first sensor (240) detecting a distance from the sound collection apparatus to an object around the sound collection apparatus to generate distant information indicative of the distance; a second sensor (230) detecting a motion of the sound collection apparatus to generate motion information indicative of the motion; a sound acquisition part (250) receiving a sound around the sound collection apparatus to generate an acoustic signal; and a controller (110) controlling collection of the acoustic signal; wherein the controller validates or invalidates the distance information based on the motion information and determines whether to collect the acoustic signal based on the distance information when the distance information is validated.
    Type: Application
    Filed: March 22, 2019
    Publication date: October 3, 2019
    Inventors: Takao ADACHI, Yoshifumi HIROSE, Yusuke ADACHI, Masahiro NAKANISHI
  • Patent number: 10269734
    Abstract: A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 23, 2019
    Assignee: ULTRAMEMORY INC.
    Inventors: Motoaki Saito, Takao Adachi
  • Publication number: 20190043537
    Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.
    Type: Application
    Filed: December 22, 2016
    Publication date: February 7, 2019
    Applicant: ULTRAMEMORY INC.
    Inventors: Yasutoshi YAMADA, Kouji UEMURA, Takao ADACHI
  • Publication number: 20180204811
    Abstract: A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element.
    Type: Application
    Filed: July 16, 2015
    Publication date: July 19, 2018
    Inventors: Motoaki SAITO, Takao ADACHI
  • Patent number: 9538375
    Abstract: Provided is a method for configuring wireless connection settings, a wireless communications apparatus, and a display method, the method being executed by the wireless communications apparatus and including: (a) receiving a first radio signal which includes second configuration information; (b) receiving authentication information for use in authenticating a first device from a second device, the authentication information being uniquely associated with the first device; (c) retaining the authentication information; (d) establishing the wireless connection with the first device, using the second configuration information; (e) transmitting a second radio signal which includes the authentication information, to the first device through the wireless connection established; (f) receiving a third radio signal which includes response information to the authentication information; and (g) transmitting the first configuration information to the first device if the response information indicates that the first device
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: January 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Masafumi Okubo, Hidetaka Oto, Keiichi Tanaka, Hiroo Ishikawa, Takao Adachi, Kohei Yamaguchi, Yuji Kunitake, Tomonori Nakamura
  • Publication number: 20150271669
    Abstract: Provided is a method for configuring wireless connection settings, a wireless communications apparatus, and a display method, the method being executed by the wireless communications apparatus and including: (a) receiving a first radio signal which includes second configuration information; (b) receiving authentication information for use in authenticating a first device from a second device, the authentication information being uniquely associated with the first device; (c) retaining the authentication information; (d) establishing the wireless connection with the first device, using the second configuration information; (e) transmitting a second radio signal which includes the authentication information, to the first device through the wireless connection established; (f) receiving a third radio signal which includes response information to the authentication information; and (g) transmitting the first configuration information to the first device if the response information indicates that the first device
    Type: Application
    Filed: June 26, 2014
    Publication date: September 24, 2015
    Inventors: Masafumi Okubo, Hidetaka Oto, Keiichi Tanaka, Hiroo Ishikawa, Takao Adachi, Kohei Yamaguchi, Yuji Kunitake, Tomonori Nakamura
  • Patent number: 8917277
    Abstract: An animation control device includes a priority identifying unit that identifies priorities of a plurality of animation parts with reference to part priority information; an animation executing unit; a determining unit that determines whether the amount of operation needed for the animation is greater than a first appropriate value; and a part control unit that changes the content of control of the animation of the change target part, which is an animation part having a low priority, from a first content of control to a second content of control when it is determined that the amount of operation needed for the animation is greater than the first appropriate value. The animation executing unit performs the animation of the change target part according to the second content of control, and performs the animation of a non-change-target part according to the first content of control.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: December 23, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Takao Adachi, Hidehiko Shin
  • Patent number: 8881059
    Abstract: A virtual object display determination unit identifies from real object display determination information a priority corresponding to a movement of a user indicated by user movement information notified by a state communication unit and, at the same time, identifies from real object attribute information a priority corresponding to a state change indicated by state change information notified by the state communication unit. By comparing the two identified priorities, the virtual object display determination unit determines whether or not to change a display mode of a virtual object. A UI generation unit generates a UI to be presented to the user based on a determination result of the virtual object display determination unit, and causes the UI to be displayed by a UI display unit.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: November 4, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventor: Takao Adachi
  • Publication number: 20140101546
    Abstract: A supported apparatus includes: an output unit that displays an operation screen which is an image including one or more operation items in the supported apparatus; a request issuance unit that issues a support start request which is a signal including operation screen information for specifying the one or more operation items displayed on the operation screen; a transmission and reception unit that transmits the support start request to a supporting apparatus, and receives guide graphical user interface (GUI) information from the supporting apparatus, the guide GUI information indicating an operation item to be operated by a supported user from among the one or more operation items; and a guide GUI superimposition unit that superimposes a guide GUI on the operation screen based on the guide GUI information, the guide GUI being an image for showing the supported user the operation item to be operated.
    Type: Application
    Filed: May 31, 2012
    Publication date: April 10, 2014
    Inventors: Yuki Taoka, Takao Adachi