Patents by Inventor Takao Fujitsu

Takao Fujitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5767572
    Abstract: A plurality of electrodes are formed on one surface of a semiconductor integrated circuit chip. A plurality of leads are arranged around the chip. Each of the electrodes and one end of each of the leads are connected. The electrodes and the chip are sandwiched between two films. One of the films is in direct contact with the one surface of the chip. The other film is in direct contact with the other surface of the chip.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: June 16, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Fujitsu
  • Patent number: 5672908
    Abstract: A plurality of electrodes are formed on one surface of a semiconductor integrated circuit chip. A plurality of leads are arranged around the chip. Each of the electrodes and one end of each of the leads are connected. The electrodes and the chip are sandwiched between two films. One of the films is in direct contact with the one surface of the chip. The other film is in direct contact with the other surface of the chip.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: September 30, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Fujitsu
  • Patent number: 5654584
    Abstract: A plurality of electrode pads are formed on a main surface of a semiconductor chip. The electrode pads on the semiconductor chip are electrically connected to the top end of an inner lead through a metal plating layer.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: August 5, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Fujitsu
  • Patent number: 5556810
    Abstract: A plurality of electrode pads are formed on a main surface of a semiconductor chip. The electrode pads on the semiconductor chip are electrically connected to the top end of an inner lead through a metal plating layer.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 17, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Fujitsu
  • Patent number: 5448106
    Abstract: A plurality of electrodes are formed on one surface of a semiconductor integrated circuit chip. A plurality of leads are arranged around the chip. Each of the electrodes and one end of each of the leads are connected. The electrodes and the chip are sandwiched between two films. One of the films is in direct contact with the one surface of the chip. The other film is in direct contact with the other surface of the chip.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: September 5, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Fujitsu
  • Patent number: 4953173
    Abstract: A semiconductor device comprises an inverted-tray-shaped support frame having a concave inner surface, a semiconductor element supported by the support frame at the center of its inner surface, and a plurality of leads which are formed on the inner surface of the support frame over an insulative layer interposed therebetween, and which extend from the center of the support frame outward to the periphery hereof and are electrically connected at their inner root ends to respective electrodes of the semiconductor element. The support frame reinforces and preserves the mechanical strength of the leads, which can therefore be spaced more closely and accurately.
    Type: Grant
    Filed: August 4, 1988
    Date of Patent: August 28, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Fujitsu