Abstract: A light modulating device includes a first transparent substrate, a second transparent substrate, a light modulating cell disposed between the first transparent substrate and the second transparent substrate, a first bonding layer disposed between the first transparent substrate and the light modulating cell, and a second bonding layer disposed between the second transparent substrate and the light modulating cell. The first bonding layer and the second bonding layer each are a bonding element containing a non-pressure-sensitive adhesive component. The first bonding layer is an OCR, and the second bonding layer is an OCA.

Abstract: A method for manufacturing a laminated glass whereby, in a laminated glass comprising a liquid crystal film sandwiched therein and having a three-dimensionally curved surface shape, the formation of wrinkles in the liquid crystal film can be suppressed; and a laminated glass which has a three-dimensionally curved surface shape and in which wrinkles in a liquid crystal film sandwiched therein are suppressed. The method for manufacturing the laminated glass comprises: a heat molding step for heating the liquid crystal film to a temperature higher than the glass transition point of the first base material layer and the second base material layer; and a bonding step for, after completing the heat molding step, heating the laminate, wherein the liquid crystal film is sandwiched between the first glass sheet and the second glass sheet, at a temperature lower than the glass transition point and bonding the same by applying a preset pressure.

Abstract: A method for manufacturing a laminated glass whereby, in a laminated glass comprising a liquid crystal film sandwiched therein and having a three-dimensionally curved surface shape, the formation of wrinkles in the liquid crystal film can be suppressed; and a laminated glass which has a three-dimensionally curved surface shape and in which wrinkles in a liquid crystal film sandwiched therein are suppressed. The method for manufacturing the laminated glass comprises: a heat molding step for heating the liquid crystal film to a temperature higher than the glass transition point of the first base material layer and the second base material layer; and a bonding step for, after completing the heat molding step, heating the laminate, wherein the liquid crystal film is sandwiched between the first glass sheet and the second glass sheet, at a temperature lower than the glass transition point and bonding the same by applying a preset pressure.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.

Abstract: A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin sealing region 9. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer 12A formed by laminating a Ni plated layer 13 and a Pd plated layer 14 in this order or a three-layer plated layer 12B formed by laminating the Ni plated layer 13, the Pd plated layer 14 and an Au plated layer 15 in this order is formed on the whole surface of the lead frame material.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.