Patents by Inventor Takao Kakiuchi
Takao Kakiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7362189Abstract: A voltage controlled current source outputs oscillator drive current and oscillator equivalent current. A signal oscillator outputs first source oscillation signal and second source oscillation signal. A differential amplifier outputs first amplification oscillation signal and second amplification oscillation signal. First switch circuit and second switch circuit output first current oscillation signal and second current oscillation signal, respectively. A first current value converter-amplifier circuit converts a value of the first current oscillation signal whereas a second current value converter-amplifier circuit converts a value of the second current oscillation signal, so that the thus converted values become output current finally. An adder outputs to the differential amplifier a differential amplifier drive current in which equivalent current for use with conversion is added up with the oscillator equivalent current outputted from the voltage controlled current source.Type: GrantFiled: May 28, 2004Date of Patent: April 22, 2008Assignee: Rohm Co., Ltd.Inventors: Takao Kakiuchi, Takeshi Wakii, Sho Maruyama
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Publication number: 20050275468Abstract: A voltage controlled current source outputs oscillator drive current and oscillator equivalent current. A signal oscillator outputs first source oscillation signal and second source oscillation signal. A differential amplifier outputs first amplification oscillation signal and second amplification oscillation signal. First switch circuit and second switch circuit output first current oscillation signal and second current oscillation signal, respectively. A first current value converter-amplifier circuit converts a value of the first current oscillation signal whereas a second current value converter-amplifier circuit converts a value of the second current oscillation signal, so that the thus converted values become output current finally. An adder outputs to the differential amplifier a differential amplifier drive current in which equivalent current for use with conversion is added up with the oscillator equivalent current outputted from the voltage controlled current source.Type: ApplicationFiled: May 28, 2004Publication date: December 15, 2005Inventors: Takao Kakiuchi, Takeshi Wakii, Sho Maruyama
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Publication number: 20050275467Abstract: A voltage controlled current source outputs oscillator drive current and oscillator equivalent current. A signal oscillator outputs first source oscillation signal and second source oscillation signal. An amplifier outputs first amplification oscillation signal and second amplification oscillation signal. First switch circuit and second switch circuit output first current oscillation signal and second current oscillation signal, respectively. A first current value converter-amplifier circuit converts a value of the first current oscillation signal whereas a second current value converter-amplifier circuit converts a value of the second current oscillation signal, so that the thus converted values become output current finally. An adder outputs to the amplifier an amplifier drive current in which equivalent current for use with conversion is added up with the oscillator equivalent current outputted from the voltage controlled current source.Type: ApplicationFiled: May 28, 2004Publication date: December 15, 2005Inventors: Takao Kakiuchi, Takeshi Wakii, Sho Maruyama
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Patent number: 5336913Abstract: A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film.Type: GrantFiled: July 17, 1992Date of Patent: August 9, 1994Assignee: Matsushita Electronics CorporationInventors: Takao Kakiuchi, Kazuo Sato
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Patent number: 5225361Abstract: A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film.Type: GrantFiled: July 9, 1991Date of Patent: July 6, 1993Assignee: Matshshita Electronics CoroprationInventors: Takao Kakiuchi, Kazuo Sato
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Patent number: 5210597Abstract: A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film.Type: GrantFiled: March 4, 1991Date of Patent: May 11, 1993Assignee: Matsushita Electronics CorporationInventors: Takao Kakiuchi, Kazuo Sato
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Patent number: 5204285Abstract: A method for patterning a metal layer without so-called "rabbit ears" comprising the steps of:deposition of a metal layer on a substrate, deposition of a barrier layer on the metal layer, formation of a mask layer of a predetermined pattern on the barrier layer, etching of the barrier layer and the metal layer under conditions such that the mask layer is also eroded slightly, and removal of the mask layer. In other embodiments, selective etching of barrier layer and mask sidewalls avoids or eliminates such "rabbit ears" and/or etchant product deposits which are precursors of such "rabbit ears".Type: GrantFiled: March 19, 1992Date of Patent: April 20, 1993Assignee: Matsushita Electronics CorporationInventor: Takao Kakiuchi
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Patent number: 5084413Abstract: A method for filling a contact hole in which (i) a silicon dioxide layer is formed on a silicon substrate; (ii) a contact hole is formed in the silicon dioxide layer; (iii) polysilicon film is formed on the side and bottom surface portions of the contact hole; (iv) gas containing tungsten reacts with the film; and (v) the contact hole is filled up with tungsten.Type: GrantFiled: May 29, 1990Date of Patent: January 28, 1992Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tsutomu Fujita, Takao Kakiuchi, Hiroshi Yamamoto, Shoichi Tanimura
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Patent number: 4988423Abstract: Disclosed is a method for fabricating an interconnection structure comprising a step of depositing an Al or Al alloy film on a dielectric film by a sputtering method improved in step coverage, a step of processing said Al or Al alloy film or a layered metal film thereof with another metal film into a metal line, and a step of depositing a film of high melting point metal or alloy thereof on the top and side surfaces of said line.Type: GrantFiled: November 3, 1989Date of Patent: January 29, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Yamamoto, Tsutomu Fujita, Takao Kakiuchi, Kousaku Yano, Shuichi Tanimura, Shinji Fujii