Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: In microwave dry etching, the substrate/resist etching selectivity is controlled by adding a material, such as an additional gas, to the reaction gas plasma that heats the substrate with greater energy transfer efficiency than the resist. For example, a W substrate having a resist is etched with an SF.sub.6 reaction gas to which is added an Xe gas for generating incident ions that impinge the substrate with greater energy transfer than they do the resist. This produces a greater hot spot temperature for the substrate as compared with the resist to increase the substrate/resist etching selectivity. The hot spot temperature difference can be further effected by applying a bias potential to the substrate during the etching with an RF power supply.