Abstract: A system-in-package semiconductor device with a CPU, a first flash memory configured to store first instructions to be executed by the CPU, and a second flash memory configured to store second instructions to be executed in accordance with a predetermined control instruction included in the first instructions. The semiconductor device determines, prior to the CPU executing the instruction, whether an instruction read out from the first flash memory is a branch instruction, and if it is determined to be the branch instruction, causes the second flash memory to perforin read-out operation using a branch destination address value indicated by the branch instruction, and if a value of a program counter of the CPU matches the branch destination address value, while the second flash memory is in a state of being ready for read-out operation in accordance with the instruction, starts reading out the second instructions from the second flash memory.

Abstract: A system-in-package semiconductor device with a CPU, a first flash memory configured to store first instructions to be executed by the CPU, and a second flash memory configured to store second instructions to be executed in accordance with a predetermined control instruction included in the first instructions. The semiconductor device determines, prior to the CPU executing the instruction, whether an instruction read out from the first flash memory is a branch instruction, and if it is determined to be the branch instruction, causes the second flash memory to perforin read-out operation using a branch destination address value indicated by the branch instruction, and if a value of a program counter of the CPU matches the branch destination address value, while the second flash memory is in a state of being ready for read-out operation in accordance with the instruction, starts reading out the second instructions from the second flash memory.

Abstract: A light emitting diode array includes a light emitting area formed on a semiconductor substrate, a diffusion prevention layer formed on the semiconductor substrate, and an insulating layer formed on the diffusion prevention layer. The diffusion prevention layer has a lower edge and the insulating layer has a level drop at this lower edge. An interconnection conductor extends on the insulating layer and is in ohmic contact with the light emitting region through holes in the insulating layer and the diffusion prevention layer. The interconnection conductor has a stepped portion at the level drop of the insulating layer, the stepped portion being located in a wide-width segment of the interconnection conductor.

Abstract: A light emitting diode array includes a light emitting area formed on a semiconductor substrate, a diffusion prevention layer formed on the semiconductor substrate, and an insulating layer formed on the diffusion prevention layer. The diffusion prevention layer has a lower edge and the insulating layer has a level drop at this lower edge. An interconnection conductor extends on the insulating layer and is in ohmic contact with the light emitting region through holes in the insulating layer and the diffusion prevention layer. The interconnection conductor has a stepped portion at the level drop of the insulating layer, the stepped portion being located in a wide-width segment of the interconnection conductor.

Abstract: An end facet light emitting type LED has a slanted light emitting side wall relative to a substrate surface. A method for manufacturing end facet light emitting type light emitting devices prevents the pn-junction regions of the devices from being damaged while a semiconductor wafer is diced to separate light emitting devices from one another. A recess is formed on the semiconductor wafer having a depth which is deeper than the pn-junction. A portion to be cut during dicing of the wafer is vertically and horizontally separated from the pn-junction regions, so that if cracks occur when the wafer is diced, the cracks do not affect the light emitting characteristics of the devices.

Abstract: In a sector mark waiting state, when a sector mark detecting signal is input to a magnetic disk controller, the magnetic disk controller initiates a write operation of sector data on a magnetic disk. In a non-sector mark waiting state, when a sector mark detecting signal is input to the magnetic disk controller, the magnetic disk controller stops the write operation of sector data upon the magnetic disk being performed.

Abstract: In a sector mark waiting stage, when a sector mark detecting signal is input to a magnetic disk controller, the magnetic disk controller initiates a write operation of sector data on a magnetic disk. In a non-sector mark waiting state, when a sector mark detecting signal is input to the magnetic disk controller, the magnetic disk controller stops the write operation of sector data upon the magnetic disk being performed.

Abstract: An information handling system for a memory includes an input section, a storage section and an output section. The information handling system is constructed to selectively provide a direct signal link between the input section and the output section without storage of the transmitted signal. Control circuits are provided to selectively cause storage of data, read-out of data, data pass-through without storage or the simultaneous carrying out of a plurality of the aforementioned operations.