Abstract: A method can record or reproduce a digital audio signal and a digital video signal simultaneously. An N-bit (N: positive integer) digital audio signal is positioned at a higher bit side and an M-bit (M: positive integer) digital video signal is positioned at a lower bit side so as to form an (N+M)-bit digital signal which is recorded or reproduced in this condition. Since the digital video signal is positioned at the lower bit side, the digital video signal may not affect the reproduced audio signal even if the (N+M)-bit digital signal is processed as the digital audio signal in the reproducing process.

Abstract: A method can record or reproduce a digital audio signal and a digital video signal simultaneously. An N-bit (N: positive integer) digital audio signal is positioned at a higher bit side and an M-bit (M: positive integer) digital video signal is positioned at a lower bit side so as to form an (N+M)-bit digital signal which is recorded or reproduced in this condition. Since the digital video signal is positioned at the lower bit side, the digital video signal may not affect the reproduced audio signal even if the (N+M)-bit digital signal is processed as the digital audio signal in the reproducing process.

Abstract: A method of simultaneously recording and reproducing a digital audio signal and a digital video signal for a dynamic picture. A digital signal is recorded and reproduced in N bits (N: integer), and an image area, an audio area and a control area are formed by part of the N bits. Compressed digital video signals for multiple screens forming a dynamic picture are allocated in the image area in each compression reference period. A digital audio signal in each compression reference period is allocated in the audio area in the compression reference period. Data, such as compression information, which concerns a digital signal to be allocated in the image area or audio area, is allocated in the control area. As a digital video signal carrying a vast amount of information is recorded in a compressed manner, and the compression information is recorded at the same time, recording and reproducing the digital video signal for a dynamic picture can be executed without problems.

Abstract: Digitally controllable ICs or function blocks in an electronic apparatus are connected through control bus lines, and a switch device is provided for disconnecting one of the digitally controllable ICs or function blocks from the control bus so that the control bus is not disabled when that one IC is turned off or is not occupied when the IC is operating in its internal processing mode. Therefore, communication between the remaining ICs can be maintained through the control bus.

Abstract: An arrangement and a method for testing various kinds of electronic equipment, each having an internal bus, during assembly and during subsequent servicing, wherein a plurality of software packages, each storing instructions and data pertinent to the testing and adjustment of a specific kind of equipment are prepared and a computer is connectable in common to the various kinds of equipment via their internal buses for testing any one of the various equipments according to the contents of the appropriate software package.

Abstract: A digital control system for electronic apparatus employs an internal bus system and includes at least one master controller and a plurality of operational circuits connected via control bus lines so that, during normal operation of the electronic apparatus, the master controller can carry out predetermined control operations relative to the respective circuit blocks. During testing and/or adjustment, an auxiliary master control circuit is connected to the control bus lines in order to control the operational circuitry in place of the master control circuit, while holding the master control in the slave mode.

Abstract: A control system for an electronic apparatus, such as a television receiver, having a control circuit with a control program in an internal memory sequentially communicates over an internal bus within predetermined intervals, such as within the vertical blanking interval of the television signal, with a plurality of controllable circuits in the television receiver, and the control circuit operates to select and communicate with a specific, selected one of the controllable circuits first, in each predetermined interval, with the remainder of the controllable circuits being subsequently communicated with in the remaining portion of the vertical blanking interval.

Abstract: A system for controlling electronic apparatus, such as a television receiver, which employs a control circuit having a control program in a read only memory to sequentially communicate over an internal system bus in a predetermined interval with a plurality of controllable, operational circuit blocks forming the electronic apparatus, in which the control circuit selects a specific circuit block for data transfer upon a request signal. In one embodiment, a request signal is transmitted prior to a vertical blanking interval in a television signal and in another embodiment, a dedicated line is provided from a selected controllable unit to the control unit, whereby the request signal can be transmitted at any time, irrespective of whether data is being transferred at such time.

Abstract: An integrated circuit device for an electronic equipment having an internal bus, the integrated circuit device comprising a digital-to-analog converter for converting a serial digital control signal to a corresponding analog control signal, a plurality of circuits subject to control in response to the analog control signal for performing specific functions, a switch circuit for selecting any one of the plurality of circuits, a switch control circuit for controlling the switch circuit to select any one of the plurality of circuits according to a received selection signal, an analog-to-digital converter for converting an output signal from the switch circuit into a corresponding digital signal, and a bus interface circuit for sending the serial digital control signal from the internal bus to the digital-to-analog converter and for sending the selection signal to the switch control circuit.

Abstract: An integrated circuit device for an electronic equipment having an internal bus, the integrated circuit device comprising a plurality of input terminals, a switch circuit connected to the plurality of input terminals for selecting any one of a respective plurality of input signals via the plurality of input terminals, a switch control circuit for controlling the switch circuit to select any one of the input signals in dependence on a selection signal, an analog-to-digital converter for converting the selected input signal from the switch circuit into a corresponding serial digital signal, and a bus interface circuit connected to the internal bus for sending the serial digital signal from the analog-to-digital converter to the internal bus and for sending the selection signal from the internal bus to the switch control circuit.

Abstract: An apparatus for scrambling or encoding a television signal by inverting the latter signal in accordance with a control signal having a predetermined code pattern comprises a detector circuit for detecting a change in a picture scene of the television signal and generating an identification signal in response to detection of the scene change and code generator for generating a key code signal of specific pattern which indicates a particular program of the television signal. According to this invention, the control signal is formed in response to both the identification signal and the key code signal.

Abstract: A television signal transmission system transmits a television signal having a polarity inverted portion in association with a scene change and a polarity inverted portion after a predetermined time interval independently of the scene change.

Abstract: A television signal receiving system for use with a scrambled television signal or a standard television signal includes a recording and reproducing circuit which records and reproduces the received television signal and a monitor for displaying the received or reproduced television signal. A descrambling circuit descrambles the scrambled television signal either as received or reproduced to generate a descrambled television signal when a detector detects the existence of a scrambled television signal and generates a control signal in response thereto. A switch responds to the control signal and automatically supplies to the monitor either the descrambled television signal or the standard television signal according to the type of television signal being received or reproduced.

Abstract: This invention relates to an apparatus for descrambling scrambled television signals including a scrambled video signal having a first scrambling pattern, a scrambled control signal having a second scrambling pattern, and descrambling signals.

Abstract: A scrambled television program is received and recorded in a scrambled fashion automatically in a video tape recorder by detecting program code signals placed in vertical blanking intervals of ten fields preceding the commencement of the scrambled program signal and upon sensing such program code signals the video tape recorder is activated to record the scrambled television program. A stop code signal is arranged following the coded television program and is detected for stopping operation of the video recorder, so that the scrambled program is recorded without requiring the manual setting of automatic timers or the like. In addition to the program code, a key code, and scene change signals are transmitted and these are used to produce a descramble pattern to descramble the television program when it is reproduced by the video tape recorder.

Abstract: Digital data transfer in a digital television receiver between an internal central processing unit, or an external computer, and the video/audio processing circuitry by way of an internal bus is accomplished efficiently and without producing noise interference by using a high-frequency clock signal and a relatively low-frequency clock signal at different times. The high-frequency signal would normally produce visually perceptable noise, however, it is employed only during vertical blanking intervals, and the low-frequency clock signal, which would not produce visually perceptable noise, is used at all times other than the vertical blanking intervals, whereby noise interference that would be otherwise seen on the visual display of the television receiver is suppressed.

Abstract: A scrambled television program that is received and recorded in a scrambled fashion includes program code and corresponding key codes for use in descrambling the recorded scrambled signal. The program codes and key codes are retained in a memory so that upon reproduction the key code can be read out of the memory and fed to a descramble pattern generator for descrambling the reproduced scrambled signal. By placing the program code and key code at the end of the scrambled program the scrambled signal cannot be descrambled until the entire program has been first received. By dividing the memory into permanent and temporary memories and adding an identification code to the transmitted scrambled signal, which selects either the permanent or temporary memory, and counting the number of times that the temporary memory is read out there can be a limitation placed on the number of times that the scrambled program is reproduced and decoded for viewing.

Abstract: A video recorder for automatically recording information being broadcast on at least one predetermined channel at a predetermined time comprises a tuner which tunes to any one of a plurality of channels received thereby and includes a channel selector actuable for selecting the predetermined channel, a recorder operable to record information broadcast on the channel to which the tuner is tuned, a timer actuable to cause operation of the recorder at the predetermined time, and a single, manually operable actuating member which simultaneously actuates the channel selector and the timer so that the recorder records the information broadcast on the predetermined channel at the predetermined time.

Abstract: A color information display apparatus includes a common memory of an integrated circuit configuration for storing both pattern data and color data describing an attribute of the corresponding pattern data to be displayed on a CRT, the common memory including a first address area for the pattern data and a second, different address area for the color data, a circuit for generating address signals for the common memories in response to the scanning position of the electron beam on the screen of the CRT, a parallel-serial converting circuit for converting parallel pattern data in the common memory to serial data, a first latch circuit for latching the color data in the common memory to produce an output color signal, a circuit for generating a color information signal from the serial data from the parallel-serial converting circuit and the output signal from the first latch circuit, an address selector connected between the address signal generating circuit and the common memory, the first address area and the s

Abstract: An AFT circuit for a television receiver automatically adjusts the frequency of a tuner local oscillator, not only on the basis of an error signal provided from an AFT discriminator, but also on the basis of horizontal synchronizing pulses contained in the video signal to which the receiver is tuned. A synch signal detector detects the presence or absence of the synchronizing pulses. A control circuit provides a control signal to the local oscillator in response to the AFT error signal when the latter is above or below a reference voltage such that the desired frequency is within an AFT capture range. However, when the AFT signal is at the reference voltage, the control circuit provides the control signal based on the presence or absence of the synchronizing pulses, such that when the pulses are present, the local oscillator frequency is raised, but when the pulses are absent, the local oscillator frequency is lowered. Then, when the AFT signal is present, the local oscillator is controlled thereby.