Abstract: A lubricating system for a machine such as a two-cycle internal combustion engine including a reciprocating pump that pumps a finite amount of lubricant during a single pumping stroke and a stepper motor for operating the pump through incremental phases of movement each less than a stroke. The lubricant requirements of the machine are determined and the driving increments are adjusted so as to provide a pumping stroke when the lubricant consumption of the machine reaches the output of the pump. Various arrangements of stepper motors and control arrangements are disclosed for controlling the amount and timing of the lubricate delivery.

Abstract: A digital signal transmission system includes a synchronization pattern detection circuit for detecting a synchronization pattern in response to a received transmitted digital signal, a pseudo synchronization detection circuit for detecting a pseudo synchronization pattern in the form of cyclic redundancy code in response to a received transmitted digital signal, and a synchronization protection circuit for counting the synchronization pattern detection signals produced when synchronization patterns are detected in response to a synchronization pattern detection signal from the synchronization pattern detection circuit. The synchronization protection circuit includes a main synchronization counter circuit and an auxiliary synchronization counter circuit. The count of protection steps for the confirmation of synchronization recovery of the auxiliary synchronization counter circuit in accordance with synchronization or asynchronization of the main synchronization counter circuit is variable.

Abstract: An asynchronous signal processing circuit device having an A-D converter and a D-A converter in which a single ladder voltage generating circuit is commonly or jointly used by changing over a multiplexer during both the A-D and the D-A conversion processing. The asynchronous signal processing circuit device according to the present invention further comprises an interrupt signal generating circuit which produces an inhibit signal so as to provide a predetermined inhibit period during which the interruption by the second signal processing circuit to the first signal processing circuit is inhibited, thus preventing a misoperation of the asynchronous signal processing circuit device at the time of switching over the converters.

Abstract: The present invention disclosed an adaptive delta modulation system which examines the several preceding bits of an output of the adaptive delta modulation, and discretely changes a quantizing stepsize of said output so as to compand the same. According to the present invention the system detects the several preceding bits of the output of the adaptive delta modulation, changes the stepsize of that output, counts the output bits of the adaptive delta modulation from the time when stepsize changes, regardless of whether the output is "0" or "1", and changes said stepsize when the counted value reaches a value which is predetermined in accordance with the quantizing stepsize at that time thereby correcting the mistracking which is generated in an adaptation logic circuit between a coder terminal and decoder terminal.

Abstract: The system according to the present invention carries out two way communication of a digital signal between a master terminal having its own clock source and a slave terminal, which is synchronized with the clock of the master terminal. The master terminal sends a digital signal originating from its own clock to the slave terminal and the slave terminal in turn sends a digital signal based on a clock signal which is derived from the received digital pulse from the master terminal.