Patents by Inventor Takao Nakashimo

Takao Nakashimo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7764056
    Abstract: Provided is a voltage control circuit which suppresses a calorific value that generates when short-circuit fault occurs even if a voltage value of an input voltage is large. At the time of short-circuit fault, an additional control voltage Va whose voltage value becomes larger when the voltage value of the input voltage Vin is larger is input to the voltage control p-channel MOS transistor (110) from a transistor control MOS transistor (160), to thereby increase resistance of the voltage control p-channel MOS transistor (110) to suppress a short-circuit current. As a result, when the input voltage Vin is larger, the current value of a holding current or a calorific value after the short-circuit protecting operation has been conducted can be suppressed.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: July 27, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Publication number: 20090243567
    Abstract: Provided is a voltage control circuit which suppresses a calorific value that generates when short-circuit fault occurs even if a voltage value of an input voltage is large. At the time of short-circuit fault, an additional control voltage Va whose voltage value becomes larger when the voltage value of the input voltage Vin is larger is input to the voltage control p-channel MOS transistor (110) from a transistor control MOS transistor (160), to thereby increase resistance of the voltage control p-channel MOS transistor (110) to suppress a short-circuit current. As a result, when the input voltage Vin is larger, the current value of a holding current or a calorific value after the short-circuit protecting operation has been conducted can be suppressed.
    Type: Application
    Filed: June 3, 2009
    Publication date: October 1, 2009
    Inventor: Takao Nakashimo
  • Patent number: 7589502
    Abstract: A charging and discharging control circuit is provided in which a delay circuit is built in an over-discharge detector circuit, an over-charge detector circuit, or the like. A delay time of the detector circuit can be changed from an external without adding a control terminal, thereby reducing a test time of the detector circuit. A voltage detector circuit is disposed between a power supply terminal and a power supply voltage detection terminal of the charging and discharging control circuit, and the voltage detector circuit detects a specified voltage or higher, to thereby shorten the delay time of the internal control circuit.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: September 15, 2009
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Publication number: 20090206807
    Abstract: Provided is a voltage regulator including an overcurrent protection circuit, which is capable of enhancing accuracy of a limit current value and a short-circuit current value, and suppressing electric power loss when an overcurrent flows through an output transistor. The overcurrent protection circuit includes: an output current detection transistor controlled by an output voltage of an error amplifier circuit, for feeding a detection current; a detection resistor for generating a detection voltage based on the detection current; a second error amplifier circuit for amplifying a difference between a voltage set by a second reference voltage and a divided voltage, and the voltage of the detection resistor, and outputting the amplified difference; and an output current limiting circuit in which a gate thereof is controlled by an output of the second error amplifier circuit, for controlling a gate voltage of the output transistor.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 20, 2009
    Inventors: Takashi Imura, Takao Nakashimo
  • Patent number: 7557556
    Abstract: Provided is a voltage control circuit which suppresses a calorific value that generates when short-circuit fault occurs even if a voltage value of an input voltage is large. At the time of short-circuit fault, an additional control voltage Va whose voltage value becomes larger when the voltage value of the input voltage Vin is larger is input to the voltage control p-channel MOS transistor (110) from a transistor control MOS transistor (160), to thereby increase resistance of the voltage control p-channel MOS transistor (110) to suppress a short-circuit current. As a result, when the input voltage Vin is larger, the current value of a holding current or a calorific value after the short-circuit protecting operation has been conducted can be suppressed.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: July 7, 2009
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Publication number: 20080136398
    Abstract: Provided is a voltage control circuit which suppresses a calorific value that generates when short-circuit fault occurs even if a voltage value of an input voltage is large. At the time of short-circuit fault, an additional control voltage Va whose voltage value becomes larger when the voltage value of the input voltage Vin is larger is input to the voltage control p-channel MOS transistor (110) from a transistor control MOS transistor (160), to thereby increase resistance of the voltage control p-channel MOS transistor (110) to suppress a short-circuit current. As a result, when the input voltage Vin is larger, the current value of a holding current or a calorific value after the short-circuit protecting operation has been conducted can be suppressed.
    Type: Application
    Filed: November 5, 2007
    Publication date: June 12, 2008
    Inventor: Takao Nakashimo
  • Publication number: 20070188142
    Abstract: Provided is a charging and discharging control circuit in which a delay circuit is built in an over discharge detector circuit, an over-charge detector circuit, or the like, and a delay time of the detector circuit can be changed from an external without adding a control terminal, thereby reducing a test time of the detector circuit. A voltage detector circuit is disposed between a power supply terminal and a power supply voltage detection terminal of the charging and discharging control circuit, and the voltage detector circuit detects a specified voltage or higher, to thereby shorten the delay time of the internal control circuit.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 16, 2007
    Inventor: Takao Nakashimo
  • Patent number: 6815940
    Abstract: A reduced power consumption diode circuit has a first voltage comparator that compares a voltage at a cathode terminal with a first sum of a voltage at an anode terminal and a voltage across a second voltage source, and outputs a reset signal. A second voltage comparator compares the voltage at the anode terminal with a second sum of the voltage at the cathode terminal and a voltage across the first voltage source, and outputs a set signal. A first latch circuit outputs a low level signal when the reset signal is input and a high level signal when the set signal is input. A diode has an anode connected to the anode terminal and a cathode connected to the cathode terminal, and an n-channel MOS transistor turns off in response to the low level signal and turns on in response to the high level signal.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: November 9, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Patent number: 6798277
    Abstract: A reference voltage circuit is provided in which a difference of voltages applied to reference voltage circuits is reduced so that a difference of respective output voltages is made small. Depletion type MOS transistors (3, 6) are respectively connected in series with the drains of depletion type MOS transistors (1, 4) in two ED type reference voltage circuits. The gate of one of the series-connected depletion type MOS transistors (3, 6) is connected with the source of the other MOS transistor and the gate of the other MOS transistor is connected with the source of the one MOS transistor. Thus, a difference of voltages applied to the respective ED type reference voltage circuits is reduced so that a difference of respective output voltages is made small.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: September 28, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Takao Nakashimo, Atsuo Fukui
  • Patent number: 6720754
    Abstract: There is provided a voltage regulator in which a ratio of a maximum current and a short circuit current is adjusted so that the maximum current is greatly increased and a short circuit current is made small. A first current limiting circuit for limiting a current value of an output voltage terminal is composed of P-channel MOS transistors (2, 4), an N-channel MOS transistor (3), and resistors (21 and 22). A second current limiting circuit for detecting a reduction in voltage of the output voltage terminal and limiting a current value of the output voltage terminal is composed of P-channel MOS transistors (2, 4), an N-channel MOS transistor (3), and resistors (20, 21, and 22). By using these circuits, the maximum current can be greatly increased and the short circuit current can be reduced.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: April 13, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Publication number: 20030174014
    Abstract: A reference voltage circuit is provided in which a difference of voltages applied to reference voltage circuits is reduced so that a difference of respective output voltages is made small. Depletion type MOS transistors (3, 6) are respectively connected in series with the drains of depletion type MOS transistors (1, 4) in two ED type reference voltage circuits. The gate of one of the series-connected depletion type MOS transistors (3, 6) is connected with the source of the other MOS transistor and the gate of the other MOS transistor is connected with the source of the one MOS transistor. Thus, a difference of voltages applied to the respective ED type reference voltage circuits is reduced so that a difference of respective output voltages is made small.
    Type: Application
    Filed: January 23, 2003
    Publication date: September 18, 2003
    Inventors: Takao Nakashimo, Atsuo Fukui
  • Patent number: 6614205
    Abstract: There is provided a charge/discharge control circuit for preventing a charging current from flowing into a secondary battery through a parasitic diode and a resistor for allowing return from an overcurrent state although a switching circuit is turned off. The present invention employs a configuration in which a connection of a charger is detected and thus the resistor is disconnected from an overcurrent detecting terminal, whereby that a charging current is prevented from flowing through the parasitic diode even when the switching circuit is turned off and the charger is connected.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Publication number: 20030107048
    Abstract: Provided is a diode circuit with small power consumption. A first voltage comparator (4) compares a voltage at a cathode terminal (101) with a sum of a voltage at an anode terminal (102) and a voltage across a first voltage source (10) to output a reset signal, and a second voltage comparator (5) compares a voltage at the anode terminal (102) with a sum of a voltage at the cathode terminal (101) and a voltage across the second voltage source (11) to output a set signal. A first latch circuit (20) outputs an L signal when the reset signal from the first voltage comparator (4) is inputted, and outputs an H signal when the set signal from the second voltage comparator (5) is inputted. An n-channel MOS transistor (2) turns off upon receiving the L signal, and turns on upon receiving the H signal, to thereby limit an output current.
    Type: Application
    Filed: November 18, 2002
    Publication date: June 12, 2003
    Applicant: Examiner for examination.
    Inventor: Takao Nakashimo
  • Patent number: 6570426
    Abstract: In a delay circuit, a voltage detecting circuit is additionally provided. This voltage detecting circuit detects such a condition that a voltage appeared at a measuring terminal of the delay circuit is shifted from a predetermined voltage range for a time duration longer than, or equal to a preset time duration. Even when the measuring terminal of the delay circuit is short-circuited to the power supply voltage, or the ground potential, this delay circuit firmly inverts the output signal level based on delay time set by an internal delay circuit.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: May 27, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Publication number: 20030090251
    Abstract: There is provided a voltage regulator in which a ratio of a maximum current and a short circuit current is adjusted so that the maximum current is greatly increased and a short circuit current is made small. A first current limiting circuit for limiting a current value of an output voltage terminal is composed of P-channel MOS transistors (2, 4), an N-channel MOS transistor (3), and resistors (21 and 22). A second current limiting circuit for detecting a reduction in voltage of the output voltage terminal and limiting a current value of the output voltage terminal is composed of P-channel MOS transistors (2, 4), an N-channel MOS transistor (3), and resistors (20, 21, and 22). By using these circuits, the maximum current can be greatly increased and the short circuit current can be reduced.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 15, 2003
    Inventor: Takao Nakashimo
  • Patent number: 6489749
    Abstract: The present invention relates to an improvement in the safety and a reduction in a current consumption in a battery device which is capable of calculating the remaining amount of a lithium ion secondary battery. If the charging and discharging current becomes equal to or lower than a given value, circuits including a current monitoring circuit operate so as to reduce the current consumption. In this situation, the current monitoring circuit stops to function. A control circuit is connected with a differentiating circuit, and if a voltage between both ends of the sense resistor changes, a charging and discharging current monitoring circuit is again operated. With the above solving means, the current consumption can be suppressed, and a precision in the current monitor can be enhanced.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: December 3, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Takao Nakashimo, Hiroshi Mukainakano
  • Publication number: 20020140474
    Abstract: In a delay circuit, a voltage detecting circuit is additionally provided. This voltage detecting circuit detects such a condition that a voltage appeared at a measuring terminal of the delay circuit is shifted from a predetermined voltage range for a time duration longer than, or equal to a preset time duration. Even when the measuring terminal of the delay circuit is short-circuited to the power supply voltage, or the ground potential, this delay circuit firmly inverts the output signal level based on delay time set by an internal delay circuit.
    Type: Application
    Filed: February 20, 2002
    Publication date: October 3, 2002
    Inventor: Takao Nakashimo
  • Publication number: 20020109483
    Abstract: There is provided a charge/discharge control circuit for preventing a charging current from flowing into a secondary battery through a parasitic diode and a resistor for allowing return from an overcurrent state although a switching circuit is turned off. The present invention employs a configuration in which a connection of a charger is detected and thus the resistor is disconnected from an overcurrent detecting terminal, whereby that a charging current is prevented from flowing through the parasitic diode even when the switching circuit is turned off and the charger is connected.
    Type: Application
    Filed: December 26, 2001
    Publication date: August 15, 2002
    Inventor: Takao Nakashimo
  • Patent number: 6373227
    Abstract: In a charging and discharging control circuit that controls the charging and discharging operation of a secondary battery and a charging type power supply device for the secondary battery which includes the charging and discharging control circuit therein, there is provided a charging and discharging control circuit that enters a test mode where the delay time of the internal control circuit is shortened when a voltage equal to or higher than a regulated voltage is applied to the charger connection terminal of a charging type power supply device.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: April 16, 2002
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo
  • Patent number: 6329795
    Abstract: A charging and discharging control circuit has a construction which limits current consumption. A plurality of detecting circuits detect at least one of an over-charge voltage and an over-discharge voltage of an electric power source and output a corresponding signal. A control circuit receives an output signal of the detecting circuits and outputs a signal for controlling the charging and discharging of the secondary batteries. In order to limit current consumption, a single source current is provided to each of the detecting circuits. In a preferred embodiment, the electric power source comprises a plurality of serially-connected batteries and the detecting circuits each comprise a comparator for comparing a reference voltage with a voltage representing an output voltage of a respective battery.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: December 11, 2001
    Assignee: Seiko Instruments Inc.
    Inventor: Takao Nakashimo