Abstract: It is an object of the present invention to provide a non-aqueous electrolyte secondary cell that is excellent in high-temperature preservation characteristics and in which an increase in the cell thickness is inhibited. The object is accomplished by the following structure. A non-aqueous electrolyte secondary cell having: a positive electrode; a negative electrode; a non-aqueous electrolyte having a non-aqueous solvent and an electrolytic salt; and an outer casing for housing the positive electrode, the negative electrode, and the non-aqueous electrolyte. The non-aqueous solvent has propylene carbonate at from 10 to 60 volume %. The non-aqueous electrolyte further has, as well as the non-aqueous solvent, vinyl acetate at from 0.3 to 3.0 mass % and vinyl ethylene carbonate at from 1.0 to 3.5 mass %.

Abstract: Input signals are processed to generate a plurality of signals having different features according to whether the input signals are speech signals or voiceband data signals, and these plural signals are entered into a neural network to be determined whether they have features closer to those of speech signals or of voiceband data signals. The classifying function of the neural network is achieved by inputting samples of speech signals and voiceband data signals and learning how to obtain correct classification results.

Abstract: Subblocks of input digital samples are stored into a buffer at frame intervals and segmented into blocks having an integral multiple of the length of the subblock. Each block is encoded into transform coefficients and stored into a memory. Each coefficient is squared and those of the squared transform coefficients which correspond to high-frequency components of the input digital samples are summed and a minimum value is detected therefrom as corresponding to an optimum block length. Those transform coefficients which correspond to the optimum block length are selected from the memory and multiplexed with a signal representative of the optimum block length. In a modification, interblock differences are detected between successive transform coefficients of equal block length and squared. Those of the squared interblock differences which correspond to equal block length are summed, producing a set of squared sums for each block length.

Abstract: This is a real time video signal processor for real time digital processing of video signals with a plurality of unit processors. All the unit processors are connected in parallel between an input bus and an output bus. Each unit processor consists of an input section connected to the input bus, a processing section for digital processing of video signals written into the input section, and an output section for supplying video signals processed by the processing section to the output bus. There is provided control sections for generating control signals to command what picture block of each frame is to be written into each unit processor and what picture block of each processed frame is to be outputted. Generally, each unit processor takes in a greater picture block than the picture block to be processed, and each processor independently accomplishes digital processing of the picture block assigned to it without communicating with any other unit processor.

Abstract: In a signal processor for processing zeroth through (N-1)-th input signal elements into zeroth through (N-1)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (11, 12) by a memory accessing arrangement which comprises a first address calculating arrangement (311, 321) for calculating a first address for the memory addresses. A distance indicating arrangement (312, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (313, 323). A pair of stored data are read from the first and the second addresses as a pair of read data.

Abstract: A succession of input signals supplied to a quantizer is processed at sampling instants into a succession of quantized codes by step sizes with a current one of the quantized codes produced at each sampling instant with reference to a current step size adaptively decided not only by a next previous quantized code and a next previous step size but also by a reference size which is determined in accordance with an average level derived from a plurality of prior quantized codes produced until production of the next previous quantized code. A decoder decodes the quantized code succession into a reproduction of the quantizer input signal succession with each quantized code decoded with reference to a similarly adaptively decided step size. It is possible that the reference step size to be determined in a digital fashion as one of a few predetermined sizes or in an analog manner to be variable between two predetermined reference sizes.

Abstract: A timing signl generator for use in a multi-processor real-time digital video processing system. Each processor in the multiprocessing system is responsible for processing a selected portion of the video picture frame, as diesignated by the timing signal generator in each processor. The timing signals include a write signal instructing the receipt of the input picture block, an execution signal instructing the processing of the picture block, and an output command signal instructing the read out of the processed picture block. The timing signal generator is composed of row and column memory circuits which are respectively addressed by row and column address counters. The counters are caused to advance in response to indications that preselected coordinates in the picture frame have been reached. As inputs, the timing signal generator receives the pixel clock as well as horizontal and vertical sync signals, the former and latter of which are counted to keep track of the current coordinates.

Abstract: A digital signal processing circuit reduces the occurrence of overflow conditions during successive arithmetic operations. The product output of a multiplication circuit is shifted by a barrel shifter to round off a predetermined number of least significant bits, thereby reducing the occurrence of an overflow condition when the successive product outputs of the multiplication circuit are summed by an arithmetic logic unit (ALU) to produce a summed output. The summed output is then shifted toward the most significant bit by a predetermined number before an output signal is generated. An overflow detection and correction circuit is provided in the event of an overflow condition occurring either to the ALU or the barrel shifter.

Abstract: In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.

Abstract: An arithmetic circuit comprises a pair of input registers for holding a pair of given numbers, and a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given numbers. This adjsutment circuit is capable of outputting at least a pair of radix point aligned fractions and one exponent derived from the radix point alignment. An arithmetic operation circuit receives the pair of the radix point aligned fractions, and outputs the result of a given arithmetic operation of the received fractions and generates an overflow signal when an overflow is generated in the arithmetic operation of the received fractions. An exponent correction circuit receives the exponent from the adjustment circuit, and is responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent. A fraction correction circuit receives the output of the arithmetic operation circuit so as to correct the received data.

Abstract: A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.

Abstract: Speech presence is detected by first comparing input signal absolute value versus a first threshold which is proportional to input signal RMS noise power, accumulating the first comparison output signal, then comparing the accumulated signal versus a second threshold signal which is proportional to a hangover time signal. The first and second threshold signals are used to form up to six threshold values.

Abstract: In an adaptive encoder encoding an encoder input signal into an encoder output signal by carrying out adaptive prediction, an encoder calculation circuit calculates electric power of an encoder electric signal related to the encoder input signal and the encoder output signal. The adaptive prediction is interrupted by an encoder interruption circuit when the electric power is not greater than a reference electric power. The electric signal may be either the encoder input signal or the encoder output signal. Preferably, a local decoded signal is monitored as the encoder electric signal by the encoder calculation circuit. When adaptive quantization is carried out in the encoder, an adaptive step size may be given as the electric signal to the encoder calculation circuit. An adaptive decoder comprises a decoder calculation circuit for calculating electric power of a decoder electric signal related to either a decoder input signal or a decoder output signal in a manner similar to the encoder calculation circuit.

Abstract: In an APDCM decoding circuit, an adaptive inverse quantizer which forms a quantized coded signal, produces a residual signal and upper and lower limits thereof. An adaptive prediction circuit uses the residual signal to predict a quantization, which is added to the other signals. The added residual is converted into a nonlinear encoded PCM for output. However the output is PCM linearized and compared to the added upper and lower limits to determine if the output should be incremented or decremented.

Abstract: An adaptive differential pulse code modulated (ADPCM) transmission system includes a subtractor for providing a difference signal E.sub.j between an input signal X.sub.j and a predicted signal X.sub.j. A coder encodes the difference signal E.sub.j into a coded signal U.sub.j for transmission to a receiver. The signal U.sub.j is also decoded at the transmitter to produce a reproduced error signal E.sub.j. A prediction circuit operates to generate a prediction signal X.sub.j on the basis of the reproduced error signal E.sub.j. The prediction circuit is controlled by a control circuit which operates to detect transmitter instability. A first level detector in the control circuit compares the input signal level against the level of a transmitter produced signal representing the input signal. A second level detector of the control circuit determines when the input signal is below a specified value.

Abstract: A digital pushbutton (PB) signalling receiver having reduced sampling frequency for reducing the operations required by digital filters. The PB receiver is responsive to an in-band audio signal digitized at a conventional sampling frequency (e.g., 8 KHz) and detects two PB frequencies, one from a lower group and one from a higher group of frequencies. The input signal is successively digitally filtered and sampled, with each sampling frequency being reduced by 1/2 from the preceeding sampling frequency. This results in two digitized outputs, both of which are much lower sampled digitized signals than the input, and each of which contains information corresponding to said lower and higher groups of frequencies, respectively. The two outputs are then applied to two banks of frequency detectors, comprising digital band-pass filters and energy calculating circuits, for providing an indication of the presence of the lower and higher group of frequencies in the original input signal.

Abstract: Overflow monitoring circuitry for an arithmetic unit offsets consecutive positive and negative overflows against one another to eliminate unnecessary overflow compensation during an arithmetic operation. In a first embodiment, an up/down counter is used to count positive overflows in one direction and negative overflows in another, with the value of the counter at the end of the arithmetic operation indicating the net overflow, if any has occurred, and the most significant bit of the counter representing the direction of any net overflow. In a second embodiment, logic circuitry offsets alternate positive and negative overflows against one another but will provide an overflow signal if either an odd number of overflows occurs or if two consecutive overflows in one direction occur during the arithmetic operation.

Abstract: A system for processing data received in the form of sample pulses has a memory with first and second major memory areas. A buffer register stores data temporarily to enable an interface between the timing of the system and of a sampled analog signal. A central processor processes data stored in one major memory area while data stored in the other major memory area is being transferred between the memory and the buffer register. The data transfer occurs during time periods while the central processor does not have access to the memory. One data item is outputted for each sample pulse received. This way, the cycle time of the sample pulses may be much greater than the cycle time of the central processor.

Abstract: A two-term vector multiplier for calculating Ax+BY and useful in FFT and digital filter circuits is disclosed. The variables A and B are converted into standard type-minimal representation codes which are then operated upon to generate selection signals and an addition-subtraction control signal. The selection signals select one of four values, X, Y, Y/2 and O, to be sent to an accumulator where the selected value is either added to or subtracted from one half the value presently in the accumulator to provide a new accumulator value. The final accumulation value is Z=AX+BY.

Abstract: An N-point DFT (discrete Fourier transform) calculator comprises a pre-processor responsive to N-point complex input data F.sub.k (k=0 to N-1) for producing N/2-point complex intermediate data G.sub.p (p=0 to N/2-1) and an N/2-point DFT calculating circuit supplied with the intermediate data as N/2-point complex input data for producing in a known manner real and imaginary parts g.sub.q.sup.R and g.sub.q.sup.I of DFT's or IDFT's (inverse DFT) g.sub.q (q=0 to N/2-1) of the latter input data G.sub.p as either real or imaginary parts f.sub.n.sup.R or f.sub.n.sup.I (n=0 to N-1) of even and odd numbered DFT's or IDFT's f.sub.2n' and f.sub.2n'+1 (n'=0 to N/2-1) of the original input data F.sub.k. The pre-processor extracts from the input data F.sub.k a truncated sequence of conjugate symmetric or antisymmetric components H.sub.m, N/2+1 in number, extracts from the truncated sequence conjugate symmetric and antisymmetric components A.sub.p and B.sub.