Patents by Inventor Takao Nomura

Takao Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210056383
    Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.
    Type: Application
    Filed: February 27, 2020
    Publication date: February 25, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi NISHI, Kumiko NOMURA, Radu BERDAN, Takao MARUKAME
  • Patent number: 10891108
    Abstract: A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the M
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 12, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Yoshifumi Nishi, Kumiko Nomura
  • Publication number: 20200302275
    Abstract: According to an embodiment, a neural network apparatus includes cores, routers, a tree path, and a short-cut path. The cores are provided according to leaves in a tree structure, each core serving as a circuit that performs calculation or processing for part of elements of the neural network. The routers are provided according to nodes other than the leaves in the tree structure. The tree path connects the cores and the routers such that data is transferred along the tree structure. The short-cut path connects part of the routers such that data is transferred on a route differing from the tree path. The routers transmit data output from each core to any of the cores serving as a transmission destination on one of routes in the tree path and the short-cut path such that the calculation or the processing is performed according to a structure of the neural network.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 24, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko Nomura, Takao Marukame, Yoshifumi Nishi
  • Publication number: 20200302274
    Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 24, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao MARUKAME, Tetsufumi TANAMOTO, Yoshifumi NISHI, Kumiko NOMURA
  • Publication number: 20200293861
    Abstract: According to an embodiment, an operation apparatus includes a first neural network, a second neural network, an evaluation circuit, and a coefficient-updating circuit. The first neural network performs an operation in a first mode. The second neural network performs an operation in a second mode and has a same layer structure as the first neural network. The evaluation circuit evaluates an error of the operation of the first neural network in the first mode and evaluates an error of the operation of the second neural network in the second mode. The coefficient-updating circuit updates, in the first mode, coefficients set for the second neural network based on an evaluating result of the error of the operation of the first neural network, and updates, in the second mode, coefficients set for the first neural network based on an evaluating result of the error of the operation of the second neural network.
    Type: Application
    Filed: August 29, 2019
    Publication date: September 17, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao MARUKAME, Yoshifumi Nishi, Kumiko Nomura
  • Publication number: 20200090037
    Abstract: According to an embodiment, a neural network device includes: a plurality of cores each executing computation and processing of a partial component in a neural network; and a plurality of routers transmitting data output from each core to one of the plurality of cores such that computation and processing are executed according to structure of the neural network. Each of the plurality of cores outputs at least one of a forward data and a backward data propagated through the neural network in a forward direction and a backward direction, respectively. Each of the plurality of routers is included in one of a plurality of partial regions each being a forward region or a backward region. A router included in the forward region and a router included in the backward region transmit the forward data and the backward data to other routers in the same partial regions, respectively.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 19, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko NOMURA, Takao MARUKAME, Yoshifumi NISHI
  • Publication number: 20200034695
    Abstract: According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 30, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Kumiko Nomura, Yoshifumi Nishi
  • Publication number: 20200026496
    Abstract: A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the M
    Type: Application
    Filed: March 7, 2019
    Publication date: January 23, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Yoshifumi NISHI, Kumiko NOMURA
  • Publication number: 20200005130
    Abstract: According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.
    Type: Application
    Filed: March 4, 2019
    Publication date: January 2, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Radu Berdan, Takao Marukame, Kumiko Nomura
  • Patent number: 10415702
    Abstract: In a parking lock system, a link member that swings due to sliding of an operating shaft so as to make a perking lock operate and release the operation includes a counterweight for canceling out axial inertial force of the operating shaft. Therefore, even if the operating shaft attempts to slide in an axial direction with respect to a transmission case due to inertial force when a vehicle experiences sudden deceleration due to a frontal collision or sudden braking, mass of the counterweight resists the inertial force to thus prevent the link member from swinging, thereby making it possible to avoid a situation in which the parking lock is operated unintentionally.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: September 17, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Takuya Nomura, Takao Ueno, Shunji Kamo
  • Publication number: 20190156180
    Abstract: According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.
    Type: Application
    Filed: March 5, 2018
    Publication date: May 23, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kumiko NOMURA, Takao Marukame
  • Publication number: 20190156181
    Abstract: According to an embodiment, a neural network device includes a control unit, and a matrix computation unit. The control unit causes a plurality of layers to execute a forward process of propagating a plurality of signal values in a forward direction, and a backward process of propagating a plurality of error values in a backward direction. The matrix computation unit performs computation on a plurality of values propagated in the plurality of layers. The matrix computation unit includes (m×n) multipliers, and an addition circuit. The (m×n) multipliers are provided in one-to-one correspondence with (m×n) coefficients included in a coefficient matrix of m rows and n columns. The addition circuit switches a pattern for adding values output from the respective (m×n) multipliers between the forward process and the backward process.
    Type: Application
    Filed: March 1, 2018
    Publication date: May 23, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao MARUKAME, Kumiko NOMURA
  • Patent number: 10199085
    Abstract: A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takao Nomura, Ryo Mori, Kazuki Fukuoka
  • Publication number: 20160064063
    Abstract: A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors.
    Type: Application
    Filed: August 4, 2015
    Publication date: March 3, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Takao NOMURA, Ryo MORI, Kazuki FUKUOKA
  • Patent number: 8201585
    Abstract: According to the present invention, even though the paint is filled or discharged repetitively to or from the paint bag (5), so that bursting of a coating bag (5) or lack of coating material during coating are not caused by accumulation of error between the filling amount and the using amount. That is, before a predetermined amount of the coating material is supplied to the coating material bag (5), the remaining coating material in the coating material bag (5) is extruded to empty it, since the coating material bag (5) is squashed by the pressure of fluid which was supplied to the hydraulic fluid chamber (6) outside of the bag.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: June 19, 2012
    Assignees: Trinity Industrial Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takao Nomura, Shigeyoshi Inada, Noriyuki Achiwa, Takanobu Mori, Kengo Honma, Akira Kato, Yasushi Ogawa
  • Patent number: 7959092
    Abstract: A coating machine enables the inside of a paint chamber to be washed clean with less amount of use of thinner by increasing washing efficiency and is capable of forming a coating with uniform coating thickness by always uniformly jetting a paint over 360° about a rotary atomizing head and the rotary atomizing head of the coating machine. The coating machine includes the rotary atomizing head in which the paint chamber is formed in the clearance between an outer bell fitted to the tip of a tubular rotating shaft and an inner bell fitted to the front side of the outer bell. Fins agitating, in the paint chamber, a washing fluid supplied from a thin tubular nozzle inserted into the tubular rotating shaft are radially formed on the rear surface side of the inner bell. An annular paint groove temporarily accumulating the paint is formed in the inner surface of the rim part of the outer bell on which the paint jetted from the paint jetting holes formed at the peripheral surface part of the paint chamber is extended.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: June 14, 2011
    Assignee: Trinity Industrial Corporation
    Inventors: Takao Nomura, Shigeyoshi Inada, Takashi Katsumata, Satoshi Takeda
  • Patent number: 7806074
    Abstract: A coating machine is capable of reducing VOC and CO2 by atomizing a paint to increase depositing efficiency without lowering production efficiency and the rotary atomizing head of the coating machine. The coating machine includes the rotary atomizing head in which a paint chamber receiving the supply of paint is formed on the rear side thereof. A plurality of rims formed in a roughly truncated conical shape for extending the paint flowing out of the paint chamber by a centrifugal force and atomizing the paint at the tip thereof are fitted in the rotary atomizing head overlappingly at specific clearances. The clearances are opened to the peripheral surface part of the paint chamber. Accordingly, VOC and CO2 can be reduced by reducing the total jetted amount of paint to enable the atomization of the paint at low rotating speeds so as the increase the deposit efficiency.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 5, 2010
    Assignee: Trinity Industrial Corporation
    Inventors: Takao Nomura, Shigeyoshi Inada, Takashi Katsumata
  • Publication number: 20090277530
    Abstract: According to the present invention, even though the paint is filled or discharged repetitively to or from the paint bag (5), so that bursting of a coating bag (5) or lack of coating material during coating are not caused by accumulation of error between the filling amount and the using amount. That is, before a predetermined amount of the coating material is supplied to the coating material bag (5), the remaining coating material in the coating material bag (5) is extruded to empty it, since the coating material bag (5) is squashed by the pressure of fluid which was supplied to the hydraulic fluid chamber (6) outside of the bag.
    Type: Application
    Filed: June 8, 2006
    Publication date: November 12, 2009
    Applicants: TRINITY INDUSTRIAL CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takao Nomura, Shigeyoshi Inada, Noriyuki Achiwa, Takanobu Mori, Kengo Honma, Akira Kato, Yasushi Ogawa
  • Publication number: 20080245296
    Abstract: A coating machine is capable of reducing VOC and CO2 by atomizing a paint to increase depositing efficiency without lowering production efficiency and the rotary atomizing head of the coating machine. The coating machine includes the rotary atomizing head in which a paint chamber receiving the supply of paint is formed on the rear side thereof. A plurality of rims formed in a roughly truncated conical shape for extending the paint flowing out of the paint chamber by a centrifugal force and atomizing the paint at the tip thereof are fitted in the rotary atomizing head overlappingly at specific clearances. The clearances are opened to the peripheral surface part of the paint chamber. Accordingly, VOC and CO2 can be reduced by reducing the total jetted amount of paint to enable the atomization of the paint at low rotating speeds so as the increase the deposit efficiency.
    Type: Application
    Filed: March 23, 2005
    Publication date: October 9, 2008
    Applicant: TRINITY INDUSTRIAL CORPORATION
    Inventors: Takao Nomura, Shigeyoshi Inada, Takashi Katsumata
  • Patent number: 7377451
    Abstract: A jet dispersing device includes a high pressure region having a flow inlet and a low pressure region having a flow outlet. A partition wall is positioned within the high pressure region such that the high pressure region is partitioned from the low pressure region. Additionally, the partition wall may be provided with at least one nozzle hole configured to jet a liquid from the high pressure region to the low pressure region such that the liquid is dispersed as fine particles. The partitioning wall may also have a cleaning fluid communication port having an opening area which is larger than an opening area of the at least one nozzle. Additionally, a valve mechanism configured to open and close the cleaning fluid communication port may also be provided.
    Type: Grant
    Filed: November 25, 2004
    Date of Patent: May 27, 2008
    Assignee: Trinity Industrial Corporation
    Inventors: Takao Nomura, Katsuhiro Ishikawa