Abstract: A power controllable wireless communication device includes a variable gain amplifier having a gain that can be controlled based on a gain control signal, a reference power generation circuit, which generates first reference power and second reference power differing from the first reference power, a sensor circuit supplied with selectively power of a high frequency signal output from the variable gain amplifier, and the first reference power and the second reference power generated by the reference power generation circuit, and a control circuit which generates the gain control signal based on a sensor output from the sensor circuit. When controlling power, the control circuit generates the gain control signal based on ratios among a first sensor output corresponding to the first reference power, a second sensor output corresponding to the second reference power, and a high frequency sensor output corresponding to the power of the high frequency signal.

Abstract: A power controllable wireless communication device includes a variable gain amplifier having a gain that can be controlled based on a gain control signal, a reference power generation circuit, which generates first reference power and second reference power differing from the first reference power, a sensor circuit supplied with selectively power of a high frequency signal output from the variable gain amplifier, and the first reference power and the second reference power generated by the reference power generation circuit, and a control circuit which generates the gain control signal based on a sensor output from the sensor circuit. When controlling power, the control circuit generates the gain control signal based on ratios among a first sensor output corresponding to the first reference power, a second sensor output corresponding to the second reference power, and a high frequency sensor output corresponding to the power of the high frequency signal.

Abstract: Provided is an amplifier with a test oscillator for a high frequency characteristic monitor, which has small power loss in a normal operation state and secures good noise performance while it is possible to equip both a transmitter IC and a receiver IC with the amplifier. In a high frequency IC including an amplifier including an inductive load and a test oscillator arranged in a same chip, the test oscillator commonly uses the inductive load of the amplifier, the amplifier has a bias voltage terminal to switch an operation state into an active state/inactive state, and the oscillator has a bias voltage terminal to switch an operation state into an active state/inactive state. In a test operation mode, the amplifier is inactivated and the test oscillator is activated and in a normal operation mode, the amplifier is activated and the test oscillator is inactivated.

Abstract: A bias circuit includes a first p-n junction element supplied with a current by a first current source connected to a low-voltage side of the first p-n junction element and a base terminal of a second transistor, a second p-n junction element supplied with a current by a second current source, the second current source connected to a low-voltage side of the second p-n junction element and a base terminal of a first transistor, the first and second transistors connected at their emitter terminals to a third current source and receiving base voltages generated by the first and second p-n junction elements, respectively. The second transistor and the first transistor constitute a differential pair in which, at a collector terminal of the second transistor, a current having a temperature coefficient that is substantially twice the temperature coefficient of the current of the second current source is obtained.

Abstract: Provided is an amplifier with a test oscillator for a high frequency characteristic monitor, which has small power loss in a normal operation state and secures good noise performance while it is possible to equip both a transmitter IC and a receiver IC with the amplifier. In a high frequency IC including an amplifier including an inductive load and a test oscillator arranged in a same chip, the test oscillator commonly uses the inductive load of the amplifier, the amplifier has a bias voltage terminal to switch an operation state into an active state/inactive state, and the oscillator has a bias voltage terminal to switch an operation state into an active state/inactive state. In a test operation mode, the amplifier is inactivated and the test oscillator is activated and in a normal operation mode, the amplifier is activated and the test oscillator is inactivated.

Abstract: A bias circuit includes a first p-n junction element supplied with a current by a first current source connected to a low-voltage side of the first p-n junction element and a base terminal of a second transistor, a second p-n junction element supplied with a current by a second current source, the second current source connected to a low-voltage side of the second p-n junction element and a base terminal of a first transistor, the first and second transistors connected at their emitter terminals to a third current source and receiving base voltages generated by the first and second p-n junction elements, respectively. The second transistor and the first transistor constitute a differential pair in which, at a collector terminal of the second transistor, a current having a temperature coefficient that is substantially twice the temperature coefficient of the current of the second current source is obtained.

Abstract: This invention provides a wireless transmitter circuit for mobile communication apparatus and this circuit can be configured with fewer components and is suitable for downsizing. A single PLL synthesizer serves as both RF frequency band PLL and IF frequency band PLL among three oscillators for TX, RX and IF frequency bands, which have been required in conventional mobile communication apparatus. The number of necessary oscillators occupying a large area within a chip is reduced and the number of components is decreased. Specifically, circuitry is arranged to generate local oscillation signals for RF and IF frequency bands by frequency dividing the output of a VCO of the RF frequency band PLL.

Abstract: A semiconductor integrated circuit device includes: a semiconductor switching element; an input voltage detection circuit that outputs a voltage correlated to an input voltage; an oscillator circuit that oscillates on the basis of the voltage outputted by the input voltage detection circuit; a control logic that generates a drive signal; a power supply circuit that boosts a battery voltage; a buffer that level-shifts the drive voltage outputted by the control logic; and an amplification element that operates using a voltage generated by the semiconductor switching element as a power supply. Thus, the semiconductor switching element can be on/off controlled so that switching loss at low load can be reduced while preventing the peak current flowing into the inductor coil from depending on the input voltage.

Abstract: A total power consumption of a radio communication apparatus is reduced, the radio communication apparatus including a semiconductor integrated circuit (high-frequency IC) which has a clock generation circuit which generates a reference clock signal for use in modulating a transmit signal and demodulating a received signal. The clock generation circuit is provided with a voltage-controlled oscillator circuit (VCXO) which oscillates, when a quartz oscillator is connected thereto, at a frequency dependent on a natural frequency of the quartz oscillator and a control voltage applied thereto. The voltage-controlled oscillator circuit is configured such that a result obtained by converting, in an internal D/A converter circuit, digital frequency control information supplied from the baseband circuit is applied as the control voltage to the voltage-controlled oscillator circuit and such that the voltage-controlled oscillator circuit oscillates at a frequency corresponding to the control voltage.

Abstract: A step-up DC/DC converter having a step-up circuit which can performs a stable control without depending on a logic threshold of a semiconductor switching device and a semiconductor integrated circuit device having the step-up DC/DC converter are provided. The step-up DC/DC converter includes: a control logic which generates a driving voltage to be supplied to a semiconductor switching device; a power supply circuit which steps-up a battery voltage to perform a level shift of the driving voltage output by the control logic; and an amplifier operated with using a voltage generated by the semiconductor switching device as a power supply. Since the level-shifted semiconductor switching device control signal is higher than a logic threshold voltage of the semiconductor switching device, the ON/OFF of the semiconductor switching device can be controlled.

Abstract: An apparatus for managing a workflow includes a workflow processing unit that includes a document generating unit that generates a circular document while setting a flow definition to make an approval route indicating a circulation order in which the circular document is to be circulated, and a transmission definition for a mail for notifying presence of the circular document to a client on the approval route, based on requests from the client, to a prototype in an operation application for generating a circular; and a proxy unit that records requests that relates to the circular document and that are transmitted from the client during circulation of the circular document, and that generates a test scenario in which the requests are arranged following the circulation order.

Abstract: An AFC-control D/A converter which controls a reference frequency oscillator is a voltage-potentiometer-type D/A converter containing three voltage followers. At least in the latter-stage voltage follower, an NMOS differential input circuit, a CMOS output circuit, and a bias circuit are supplied with an external power voltage. However, PMOS differential input circuit is supplied with an internal regulated power supply voltage generated by a reference voltage generator. Even if there is a shift in the pair nature of MP1 and MP2 of the differential PMOS, an increase of current of MP3 of a PMOS current source due to the increase of the external power voltage is suppressed. Also an input offset voltage of the differential PMOS does not increase, and a change of an AFC control analog output signal can be reduced.

Abstract: A workflow-management apparatus includes a print-of-a-seal form defining unit 21 for receiving registration of form information specifying a form of a print of a seal and for receiving a change of the form information, and a print-of-a-seal image creating unit 26 for creating a print-of-a-seal image according to form information registered in the print-of-a-seal form defining unit 21. The workflow-management apparatus can add a print-of-a-seal image to a circulating electronic document.

Abstract: A total power consumption of a radio communication apparatus is reduced, the radio communication apparatus including a semiconductor integrated circuit (high-frequency IC) which has a clock generation circuit which generates a reference clock signal for use in modulating a transmit signal and demodulating a received signal. The clock generation circuit is provided with a voltage-controlled oscillator circuit (VCXO) which oscillates, when a quartz oscillator is connected thereto, at a frequency dependent on a natural frequency of the quartz oscillator and a control voltage applied thereto. The voltage-controlled oscillator circuit is configured such that a result obtained by converting, in an internal DA converter circuit, digital frequency control information supplied from the baseband circuit is applied as the control voltage to the voltage-controlled oscillator circuit and such that the voltage-controlled oscillator circuit oscillates at a frequency corresponding to the control voltage.

Abstract: The communication semiconductor integrated circuit includes serial-signal processing circuits having low-pass filters and variable gain amplifier circuits cascade-connected in series. The low-pass filters constituting the serial-signal processing circuit each include a variable capacitance circuit composed of capacitance elements and switching elements connected in series to the capacitance elements, respectively, and capable of selecting the capacitance elements to change capacitance of the low-pass filter. A reference clock signal is supplied to the circuit containing the low-pass filters upon turning on of a power supply, for example, to determine a deviation of a delay time in the circuit to a design value and on and off states of the switching elements of the variable capacitance circuit are set so that the deviation of the delay time is minimized.

Abstract: This invention provides a wireless transmitter circuit for mobile communication apparatus and this circuit can be configured with fewer components and is suitable for downsizing. A single PLL synthesizer serves as both RF frequency band PLL and IF frequency band PLL among three oscillators for TX, RX and IF frequency bands, which have been required in conventional mobile communication apparatus. The number of necessary oscillators occupying a large area within a chip is reduced and the number of components is decreased. Specifically, circuitry is arranged to generate local oscillation signals for RF and IF frequency bands by frequency dividing the output of a VCO of the RF frequency band PLL.

Abstract: In a semiconductor integrated circuit having a plurality of electronic circuits each provided with interfaces used for effecting signal transmission, and supplied with operating voltages from a plurality of independent power supply terminals, protective elements each having high threshold voltages at which the elements are off in the ordinary state of power supply are provided, and a resistor and a diode both for preventing electrostatic breakdown are connected to the gate of an input MOSFET of the interface for carrying out signal transmission between the electronic circuits. Even when a high voltage due to static electricity is applied to each power supply terminal while the semiconductor integrated circuit is handled, electrostatic breakdown of the interface can be prevented by the protective element or the electrostatic breakdown preventive circuit comprising a resistor and a diode.

Abstract: The number of current sources and switches necessary for a plurality of unit D/A converters using equal reference currents, are drastically reduced to reduce the parasitic capacitance coupled to current output lines, by converting a plurality of digital signals of a predetermined bit, which are divided from an input digital signal, into an analog current unit D/A converters and by converting the analog current in a manner to correspond to the weights of the corresponding input digital signals, thereby to synthesize the currents. The fixed reference digital signal is inputted to the D/A converter for cancelling offsets. The offsets of a plurality of analog output signals in positive and opposite phases obtained by branching the output of the D/A converter are individually detected. After this, the DC offset values of the individual analog outputs are used as offset adjusted negative feedback signals for a desired value.

Abstract: A constant current is produced by a first MOSFET of depletion type whose source and gate are interconnected and then is passed through a current mirror circuit made up of MOSFETs of the opposite conduction type with respect to the first MOSFET and to a second MOSFET which has the same conduction type as the first MOSFET and whose gate and drain are interconnected. The voltage between the gate and the source of the second MOSFET is taken as an output constant voltage, which is temperature-compensated by the current ratio of the current mirror circuit.

Abstract: A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.