Patents by Inventor Takao Oono

Takao Oono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210402357
    Abstract: An embodiment of the present invention provides a polyolefin microporous membrane, including: a first porous layer containing a polyolefin and having a structure including a first rod-shaped crystal extending in one direction and plural first plate-shaped crystals arranged in a separated state and intersecting the first rod-shaped crystal, and a second porous layer containing a polyolefin and having a structure including a second rod-shaped crystal extending in another direction intersecting the one direction and plural second plate-shaped crystals arranged in a separated state and intersecting the second rod-shaped crystal.
    Type: Application
    Filed: October 29, 2019
    Publication date: December 30, 2021
    Applicant: Teijin Limited
    Inventors: Yoshikazu IKUTA, Koji FURUYA, Takao OONO
  • Patent number: 5088065
    Abstract: Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
    Type: Grant
    Filed: October 5, 1990
    Date of Patent: February 11, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Shoji Hanamura, Masaaki Kubotera, Katsuro Sasaki, Takao Oono, Kiyotsugu Ueda
  • Patent number: 4891792
    Abstract: Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
    Type: Grant
    Filed: July 6, 1988
    Date of Patent: January 2, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Shoji Hanamura, Masaaki Kubotera, Katsuro Sasaki, Takao Oono, Kiyotsugu Ueda