Patents by Inventor Takao Ozeki
Takao Ozeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8331157Abstract: First main bit lines correspond to at least one first memory cell. Second main bit lines correspond to at least one second memory cell. At least one sense amplifier outputs read data according to a difference between a voltage of any one of the first main bit lines and a voltage of any one of the second main bit lines. A voltage supply switching section supplies a predetermined reference voltage to one of the first main bit lines corresponding to one of the second main bit lines in which a current according to a threshold voltage of the at least one second memory cell is generated. A resistance switching section forms electrical connection between a ground node and the one of the second main bit lines in which the current according to the threshold voltage of the at least one second memory cell is generated with a predetermined resistance value.Type: GrantFiled: January 26, 2011Date of Patent: December 11, 2012Assignee: Panasonic CorporationInventor: Takao Ozeki
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Publication number: 20110122677Abstract: First main bit lines correspond to at least one first memory cell. Second main bit lines correspond to at least one second memory cell. At least one sense amplifier outputs read data according to a difference between a voltage of any one of the first main bit lines and a voltage of any one of the second main bit lines. A voltage supply switching section supplies a predetermined reference voltage to one of the first main bit lines corresponding to one of the second main bit lines in which a current according to a threshold voltage of the at least one second memory cell is generated. A resistance switching section forms electrical connection between a ground node and the one of the second main bit lines in which the current according to the threshold voltage of the at least one second memory cell is generated with a predetermined resistance value.Type: ApplicationFiled: January 26, 2011Publication date: May 26, 2011Applicant: PANASONIC CORPORATIONInventor: Takao OZEKI
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Publication number: 20070118719Abstract: There is provided a method for controlling a semiconductor memory which includes a memory cell array including a plurality of multivalued memory cells where, in each of the memory cells, a first write operation allows storage of data in a first page address and a second write operation allows storage of data in a second page address, the method comprising an address conversion table processing step and an address scramble step. At the address conversion table processing step, an address conversion table for address conversion is generated by, in each of the plurality of multivalued memory cells, allocating addresses in which writing is to be performed to addresses such that data is written in a second page address after writing of data in a first page address. At the address scramble step, address conversion is performed on an input address according to the address conversion table.Type: ApplicationFiled: November 13, 2006Publication date: May 24, 2007Inventors: Takao Ozeki, Makoto Arita, Kunisato Yamaoka, Shunichi Iwanari
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Patent number: 7161832Abstract: A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.Type: GrantFiled: June 3, 2005Date of Patent: January 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Junichi Kato, Masayoshi Nakayama, Takao Ozeki, Asako Miyoshi, Shinichi Hatakeyama
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Patent number: 7075839Abstract: A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.Type: GrantFiled: April 12, 2004Date of Patent: July 11, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Mukunoki, Akira Sugimoto, Takao Ozeki
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Publication number: 20050276103Abstract: A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.Type: ApplicationFiled: June 3, 2005Publication date: December 15, 2005Inventors: Junichi Kato, Masayoshi Nakayama, Takao Ozeki, Asako Miyoshi, Shinichi Hatakeyama
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Publication number: 20040208071Abstract: A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.Type: ApplicationFiled: April 12, 2004Publication date: October 21, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshio Mukunoki, Akira Sugimoto, Takao Ozeki
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Patent number: 6638015Abstract: A water pump apparatus includes a body adapted to a fixed mounting surface of an engine and having a bore, a rotational shaft rotatably supported on the body via a bearing, an impeller fixed to the shaft and located in a pump chamber for supplying forcibly water from a water inlet to a water outlet, a seal member for sealing between the pump chamber and the bore of the body and a collection chamber portion provided on at least one of the body or the engine so as to communicate with the bore between the bearing and the seal member via a drain passage and for collecting water leaked via the seal member, wherein the collection chamber portion is opened toward the mounting surface of the engine and an opening of the collection chamber portion is fluid-tight closed by fixing the body to the engine.Type: GrantFiled: March 25, 2002Date of Patent: October 28, 2003Assignee: Aisin Seiki Kabushiki KaishaInventors: Yasuo Ozawa, Junya Yamamoto, Masaki Chujo, Takao Ozeki
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Publication number: 20020136633Abstract: A water pump apparatus includes a body adapted to a fixed mounting surface of an engine and having a bore, a rotational shaft rotatably supported on the body via a bearing, an impeller fixed to the shaft and located in a pump chamber for supplying forcibly water from a water inlet to a water outlet, a seal member for sealing between the pump chamber and the bore of the body and a collection chamber portion provided on at least one of the body or the engine so as to communicate with the bore between the bearing and the seal member via a drain passage and for collecting water leaked via the seal member, wherein the collection chamber portion is opened toward the mounting surface of the engine and an opening of the collection chamber portion is fluid-tight closed by fixing the body to the engine.Type: ApplicationFiled: March 25, 2002Publication date: September 26, 2002Inventors: Yasuo Ozawa, Junya Yamamoto, Masaki Chujo, Takao Ozeki