Patents by Inventor Takao Saitoh
Takao Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12041820Abstract: In a method for manufacturing an active matrix substrate, forming of an underlayer inorganic insulating film includes applying a resist onto the underlayer inorganic insulating film, performing an ashing process of forming a surface having irregularities on a surface of the resist by a first ashing process, and, after the ashing process has been performed, roughening a surface of the underlayer inorganic insulating film by performing a second ashing process and an etching process on the underlayer inorganic insulating film. When forming a semiconductor film, a surface of at least a part of the semiconductor film is roughened following a rough surface of the underlayer inorganic insulating film.Type: GrantFiled: September 6, 2018Date of Patent: July 16, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki, Yi Sun, Masaki Yamanaka, Seiji Kaneko
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Publication number: 20240237434Abstract: In an organic EL display device, a frame region provided outside a display region is provided with a damming wall extending on an outer periphery of the display region and a second lead-out wiring line extending across the damming wall from the display region side to an outside of the frame region. The damming wall includes a bank portion having a projecting shape and provided, in a part in which the second lead-out wiring line extends, on both sides in a direction in which the second lead-out wiring line extends with respect to a top portion of the damming wall. The bank portion is lower than a top portion of a second damming wall and forms, between the bank portion and the top portion, a trap portion having a recessed shape.Type: ApplicationFiled: March 25, 2021Publication date: July 11, 2024Inventors: Takao SAITOH, Yohsuke KANZAKI, Masaki YAMANAKA, Masahiko MIWA, Yi SUN, Masaki FUJIWARA
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Patent number: 12029083Abstract: A first metal layer that is formed by a first metal film is provided in an island shape along a pair of third wiring lines that is adjacent to each other. The first metal layer overlaps a region that is surrounded by a pair of first wiring lines, among several first wiring lines extending parallel to each other and formed by a first metal film, that is adjacent to each other, and the pair of third wiring lines, among several third wiring lines extending parallel to each other and in a direction intersecting each of the several first wiring lines.Type: GrantFiled: September 21, 2018Date of Patent: July 2, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masahiko Miwa, Masaki Yamanaka, Yohsuke Kanzaki, Seiji Kaneko, Yi Sun
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Publication number: 20240206251Abstract: A display device of the present disclosure has a display region including a thin-film transistor, a terminal section, and a bending portion provided between the display region and the terminal section, and the display device includes the following: a resin layer provided above a base in the bending portion; an insulating layer provided to cover the resin layer; and a first wire provided above the insulating layer and extending in a first direction to electrically connect the thin-film transistor and the terminal section together, the first direction being a direction where the display region and the terminal section are disposed, wherein in the bending portion, the resin layer has at least one hole or dent overlapping the first wire in a plan view, and the insulating layer has at least one opening overlapping the at least one hole or dent in a plan view.Type: ApplicationFiled: April 21, 2020Publication date: June 20, 2024Inventors: Takao SAITOH, Yohsuke KANZAKI, Masaki YAMANAKA, Yi SUN, Masahiko MIWA
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Patent number: 11996418Abstract: A display device includes a substrate; a semiconductor layer; a gate insulating film; a gate electrode; a first interlayer insulating film; a capacitance electrode; and a second interlayer insulating film. Each of a pixel circuits includes a drive transistor, a capacitor and a connection wiring line. The capacitance electrode is provided with a first opening and a second opening in portions of positions overlapping with the gate electrode in plan view. The first interlayer insulating film and the second interlayer insulating film include a contact hole provided at a position surrounded by the first opening and a hole provided at a position surrounded by the second opening. The connection wiring line is provided on the second interlayer insulating film and is connected to the gate electrode via the contact hole. The hole overlaps with a portion of a channel region in plan view.Type: GrantFiled: April 9, 2019Date of Patent: May 28, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Miwa, Takao Saitoh, Masaki Yamanaka, Yi Sun, Yohsuke Kanzaki
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Patent number: 11985876Abstract: First overlying wires are provided between a display area and a bending portion, extending parallel to each other in a direction crossing the direction in which the bending portion extends. Underlying wires are provided between a first resin layer and a second resin layer on a resin substrate, extending across a slit and parallel to each other in a direction crossing the direction in which the bending portion extends. The first overlying wires are electrically connected respectively to the underlying wires via first contact holes formed through the second resin layer and inorganic insulation films.Type: GrantFiled: July 20, 2018Date of Patent: May 14, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki, Yi Sun, Masaki Yamanaka, Seiji Kaneko
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Publication number: 20240155901Abstract: A second test portion includes a second test first terminal, a second test second terminal, a second test third terminal, and a second test fourth terminal electrically connected to a second test semiconductor layer via respective contact holes formed in a layered film of a gate insulating film and an interlayer insulating film, and the layered film of the gate insulating film and the interlayer insulating film in the second test portion is provided with an opening open upward between at least one of the second test first terminal, the second test second terminal, the second test third terminal, and the second test fourth terminal.Type: ApplicationFiled: March 25, 2021Publication date: May 9, 2024Inventors: Takao SAITOH, Yohsuke KANZAKI, Masaki YAMANAKA, Masahiko MIWA, Yi SUN, Masaki FUJIWARA
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Publication number: 20240155883Abstract: A display device includes a display panel including a base substrate layer, a thin film transistor layer, a light-emitting element layer, and a sealing film, and includes an image capturing unit provided on the base substrate layer side of a display region of the display panel. A plurality of subpixels constituting the display region are divided into a group of normal subpixels provided so as not to overlap with the image capturing unit and a group of thinned-out subpixels provided so as to overlap with the image capturing unit. The inorganic insulating film is provided with openings passing through the inorganic insulating film, in an image capturing region overlapping with the group of thinned-out subpixels.Type: ApplicationFiled: March 26, 2021Publication date: May 9, 2024Inventors: Takao SAITOH, Yohsuke KANZAKI, Masaki YAMANAKA, Masahiko MIWA, Yi SUN, Masaki FUJIWARA
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Publication number: 20240138212Abstract: In an organic EL display device, a frame region provided outside a display region is provided with a damming wall extending on an outer periphery of the display region and a second lead-out wiring line extending across the damming wall from the display region side to an outside of the frame region. The damming wall includes a bank portion having a projecting shape and provided, in a part in which the second lead-out wiring line extends, on both sides in a direction in which the second lead-out wiring line extends with respect to a top portion of the damming wall. The bank portion is lower than a top portion of a second damming wall and forms, between the bank portion and the top portion, a trap portion having a recessed shape.Type: ApplicationFiled: March 24, 2021Publication date: April 25, 2024Inventors: Takao SAITOH, Yohsuke KANZAKI, Masaki YAMANAKA, Masahiko MIWA, Yi SUN, Masaki FUJIWARA
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Patent number: 11968866Abstract: A second connection wire is electrically connected to a first connection wire via a display-side contact portion and terminal-side contact portion in a bending section. The first connection wire and the second connection wire do not overlap each other at least partly between the display-side contact portion and terminal-side contact portion.Type: GrantFiled: June 20, 2019Date of Patent: April 23, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Yohsuke Kanzaki, Yi Sun, Takao Saitoh, Masahiko Miwa, Masaki Yamanaka
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Patent number: 11903299Abstract: A TEG near the perimeter of a frame region is away from a TFT, which is disposed in a display region and is actually used for screen display. Hence, the characteristics of the TEG can change in a manner different from that in the characteristics of the TFT within the display region. Accordingly, provided is a display device that includes a TEG pattern disposed between the display region and a trench, and includes a dummy pixel circuit disposed between the display region and a barrier wall. The TEG pattern is outside the display region and is adjacent to at least the dummy pixel circuit.Type: GrantFiled: November 16, 2018Date of Patent: February 13, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masahiko Miwa, Masaki Yamanaka, Yi Sun, Yohsuke Kanzaki, Seiji Kaneko
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Patent number: 11871615Abstract: A display device includes: a base substrate; a TFT layer including a plurality of pixel circuits arranged; and a light-emitting element layer. Each of the plurality of pixel circuits includes: a TFT including a semiconductor layer, a gate insulating film, and a gate electrode; and a capacitor including the gate electrode, a first inorganic insulating film, and a capacitive electrode. The capacitive electrode extends all around a perimeter of the gate electrode and extends to an outside of the perimeter. An angle formed between an upper surface of the base substrate and at least a part of an end surface in a circumferential direction of the gate electrode not overlapping the semiconductor layer in the plan view is greater than an angle formed between the upper surface of the base substrate and an end surface of the gate electrode overlapping the semiconductor layer in the plan view.Type: GrantFiled: December 7, 2018Date of Patent: January 9, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki, Masaki Yamanaka, Yi Sun
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Publication number: 20230413615Abstract: According to an aspect pf the disclosure, a display device includes a base substrate; a thin film transistor layer provided on the base substrate and including a wiring layer; and a light-emitting element layer provided on the thin film transistor layer and including a plurality of first electrodes, a plurality of functional layers, and a common, second electrode, which are sequentially stacked in such a manner as to correspond to a plurality of subpixels in a display area.Type: ApplicationFiled: September 23, 2020Publication date: December 21, 2023Inventors: TAKAO SAITOH, YOHSUKE KANZAKI, MASAKI YAMANAKA, YI SUN, MASAHIKO MIWA
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Publication number: 20230329038Abstract: A capacitor (9ha) includes a gate electrode (14a), a first interlayer insulating film (15), a capacitance electrode (16c), and a capacitance wiring line (18ha). The capacitance wiring line (18ha) is electrically connected to the capacitance electrode (16c). A capacitance of the capacitor (9ha) is formed between the gate electrode (14a) and the capacitance electrode (16c) and the capacitance wiring line (18ha) arranged facing each other across the first interlayer insulating film (15). A line width (W18h) of the capacitance wiring line (18ha) is equal to or greater than a line width (W16c) of the capacitance electrode (16c) and equal to or less than a line width (W14a) of the gate electrode (14a).Type: ApplicationFiled: September 8, 2020Publication date: October 12, 2023Inventors: TAKAO SAITOH, YOHSUKE KANZAKI, MASAKI YAMANAKA, MASAHIKO MIWA, YI SUN
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Publication number: 20230276667Abstract: A display device includes a base substrate, a thin film transistor layer and a light-emitting element layer. An insular non-display area is provided internal to a display area. A through hole extends in a direction of a thickness of the base substrate in a non-display area. A separation wall is provided in the non-display area so as to surround the through hole. The separation wall includes: a wall base portion made of a same material and in a same layer as a planarization film and provided like a frame; and a wall top portion made of a same material and in a same layer as an inorganic insulation film and provided on the wall base portion like a brim projecting from a display area side toward a through hole side.Type: ApplicationFiled: July 22, 2020Publication date: August 31, 2023Inventors: TAKAO SAITOH, YOHSUKE KANZAKI, MASAKI YAMANAKA, YI SUN
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Patent number: 11699778Abstract: A display device includes: an underlayer, a first insulating film contacting an upper face of the underlayer, a semiconductor layer, a second insulating film, a first metal layer, a first resin layer, a first electrode, and a second resin layer, in order from a lower layer, wherein at least one of the underlayer, the first resin layer, and the second resin layer is a thin film layer having a maximum film thickness in a display region provided with a light-emitting element being thicker than a maximum film thickness in a frame region surrounding the display region.Type: GrantFiled: March 16, 2018Date of Patent: July 11, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Yi Sun, Yohsuke Kanzaki, Masaki Yamanaka, Masahiko Miwa, Seiji Kaneko
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Patent number: 11681388Abstract: A display device includes a plurality of upper layer electrodes including a first upper layer electrode and a second upper layer electrode electrically separated from the first upper layer electrode, and a lower layer electrode provided in common with the first upper layer electrode and a second upper layer electrode and overlapping with the first upper layer electrode and the second upper layer electrode via an insulating film. The first upper layer electrode includes a first protrusion protruding toward the second upper layer electrode, and the second upper layer electrode includes a second protrusion protruding toward the first upper layer electrode. The lower layer electrode is provided with a wide portion having a width greater than those of the first protrusion and the second protrusion, the wide portion overlapping at least with a gap between the first protrusion and the second protrusion.Type: GrantFiled: April 19, 2019Date of Patent: June 20, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Masaki Yamanaka, Yi Sun, Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki
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Patent number: 11659746Abstract: A first wiring line and a second wiring line are extended to an upper face of a resin substrate exposed from a slit formed in at least one layer of an inorganic insulating film, a first flattening film is provided within the slit which exposes the upper face of the resin substrate between the portions to which the first wiring line and the second wiring line are extended, and the first wiring line and the second wiring line are electrically connected to each other via a third wiring line provided between an end face of the first flattening film and the upper face of the resin substrate.Type: GrantFiled: March 9, 2018Date of Patent: May 23, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Seiji Kaneko, Yohsuke Kanzaki, Masahiko Miwa, Masaki Yamanaka, Yi Sun
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Publication number: 20230152647Abstract: A display device of the present disclosure has the following: a display region including a thin-film transistor; a frame region surrounding the display region; a terminal section provided in the frame region; a resin layer provided above a base; an inorganic insulating layer provided on the resin layer and having an opening; and a conductive pattern provided on the inorganic insulating layer in a location except a location over the opening.Type: ApplicationFiled: April 20, 2020Publication date: May 18, 2023Inventors: Yohsuke KANZAKI, Takao SAITOH, Masahiko MIWA, Masaki YAMANAKA, Yi SUN
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Patent number: 11650469Abstract: A method for manufacturing a display device includes a pixel circuit formed on a substrate, wherein a manufacturing process of the pixel circuit includes a patterning step of a metal film performed in the following procedures (a) to (e): (a) forming the metal film on the substrate; (b) forming a first resist pattern on the metal film by a photolithographic method; (c) etching the metal film with the first resist pattern to form a first metal pattern; (d) forming by the photolithographic method on the metal film formed in the first metal pattern, a second resist pattern including a pattern shape smaller than a pattern shape of the first resist pattern; and (e) etching the metal film with the second resist pattern to form a second metal pattern.Type: GrantFiled: March 28, 2018Date of Patent: May 16, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Yohsuke Kanzaki, Takao Saitoh, Masahiko Miwa, Masaki Yamanaka, Yi Sun, Seiji Kaneko