Patents by Inventor Takao Satoh

Takao Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6212671
    Abstract: A well wall of a second type of conduction is formed so as to surround a first IC formed in a first IC forming region specified by a region specifying means and to extend from a surface of a semiconductor substrate to a bottom well on the basis of information about the first IC forming region and information about the bottom well in a mask pattern produced by a bottom well mask pattern producing means.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: April 3, 2001
    Assignees: Mitsubishi Electric System LSI Design Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yusuke Kanehira, Takao Satoh, Nobuhide Naritomi
  • Patent number: 6108750
    Abstract: A disk storage system has a control unit having a plurality of external connection points. When the control unit receives two read requests issued from a processor to two disks of a disk unit group, a first read operation is performed to read data requested by the first read request from one of the disks and a second read operation is performed to read data requested by the second read request from the other one of the disks. Also, a first output operation is performed to output data read by the first read operation from one of the external connection points of the control unit and a second output operation is performed to output data read by the second read operation from another of the external connection points of the control unit. The second output operation is started before the first output operation has finished.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 6098191
    Abstract: An intermediate value derived from old and new data record values or old and new data themselves are sent from a control unit to a disk unit which stores a parity record as information necessary for updating parity. The disk unit reads an old parity record and generates a new value of parity record based on the read old parity and the information received from the control unit. The generated new value is stored in an empty record on the storage medium to which a read/write head is first positioned after the generation of the new value and in which effective data has not been stored. In a disk array system, a time required to update the parity record due to the updating of the data record is reduced and a performance of the storage unit subsystem is improved.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: August 1, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Yasutomo Yamamoto, Manabu Kitamura, Takao Satoh
  • Patent number: 5979475
    Abstract: A highly clean fluid treatment system having a small system volume is provided by using a Bernoulli holder to accomplish stable holding of a specimen in a simple configuration. A holder having a specimen hold face formed almost the same as a specimen or having a Bernoulli effect producing region and a region surrounding the Bernoulli region made of a specific combination of materials is used and fluid supply sources are connected to the holder for supplying one or more fluids containing a treatment agent of a specimen. Since a force for inhibiting a position shift occurs on the end face of the specimen 10, stable specimen holding is enabled. The space between the specimen and the holder where treatment is executed is narrow and fluid always flows from the treatment space to the outside. Therefore, the fluid treatment system of a small volume producing high treatment efficiency and minimizing the chances of recontamination of the specimen can be provided.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: November 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Takao Satoh, Haruo Itoh, Hitoshi Oka, Yoichi Takahara, Akio Saito
  • Patent number: 5958078
    Abstract: An intermediate value derived from old and new data record values or old and new data themselves are sent from a control unit to a disk unit which stores a parity record as information necessary for updating parity. The disk unit reads an old parity record and generates a new value of parity record based on the read old parity and the information received from the control unit. The generated new value is stored in an empty record on the storage medium to which a read/write head is first positioned after the generation of the new value and in which effective data has not been stored. In a disk array system, a time required to update the parity record due to the updating of the data record is reduced and a performance of the storage unit subsystem is improved.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: September 28, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Yasutomo Yamamoto, Manabu Kitamura, Takao Satoh
  • Patent number: 5956750
    Abstract: A storage controller calculates an access frequency of each logical disk; that it selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical devices to the second and the first physical disk devices, respectively.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: September 21, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yasutomo Yamamoto, Akira Yamamoto, Takao Satoh
  • Patent number: 5835938
    Abstract: For a write request from the CPU, the control unit selects a specific disk unit in the disk unit group for the immediate writing of data. In a second kind of load distribution a disk unit is selected to execute read and staging other than the above-mentioned specific disk.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: November 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 5751937
    Abstract: A storage unit system includes a control apparatus having a unit for reading memory data from a plurality of storage units before increase into a memory of the control apparatus, a preparing unit for preparing parity data newly from the memory data read in the memory, a rearrangement unit for dispersing transfer data from a processor read in the memory and the newly prepared parity data to be written into a plurality of storage units after the increase to perform arrangement of data, a memory unit for storing a write position on the way of the rearrangement of data, a comparison unit for comparing an access position for an access request from the processor with the write position, and a determining unit for determining a data dispersed pattern used in a data access from the processor on the basis of a comparison result of the comparison means, whereby the storage unit can be increased individually with a unit of one storage unit and dynamically without stop of the system.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: May 12, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Kouji Arai, Takao Satoh, Akira Yamamoto
  • Patent number: 5734813
    Abstract: In this invention a logical record represents a record accessed by a HOST computer. A physical record represents a record defined on disk units. Physical records consist of data records and parity records. A data record has a value of a logical record. m data records and n parity records form parity records. Parity records are utilized to recover the contents of the data records which belong to the same parity group. A reduction in the generation times of updated values of parity records is realized. A data value of parity records has an allocated status to a logical record and an unallocated status. When a parity-generation scheduling unit decides generation of updated values of a parity group, it recognizes data records which are unallocated to logical records in the parity groups. Then it searches the logical records which are allocated to data records included in the other parity group. Finally it reallocates the recognized data records to the searched logical records.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Yasutomo Yamamoto, Hisaharu Takeuchi, Takao Satoh
  • Patent number: 5680574
    Abstract: The control unit arbitrarily selects a disk unit among the disk units that are inactive when the control unit receives an input/output request involving either read or staging. For a write request, the control unit selects a master disk unit in the disk unit group for the immediate writing of data, and a disk unit other than the above-mentioned master disk is preferably selected to execute the read and staging unit. After writing is used to write the data into the other disk units after the write request execution is completed by writing to the master disk unit.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: October 21, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 5664096
    Abstract: A disk array controller is connected to both a host computer and a plurality of disk drives operating in parallel. The disk array controller is responsive to an output request from the host computer for dividing data supplied from the host computer and parallel writing the divided data in the plurality of disk drives. In response to an input request from the host computer, the disk array controller combines data parallelly read from the disk drives into a set of data. Responsive to the output request, a processor stores in a non-volatile memory a write status of each block within a data write area for each disk drive to which data is to be written. The write status includes a first status representing a write completed status of each disk drive, a second status representing a writing status of each disk drive, and a third status representing a no write indication status of each disk drive.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: September 2, 1997
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.
    Inventors: Hiroshi Ichinomiya, Takao Satoh, Akira Yamamoto
  • Patent number: 5640600
    Abstract: A storage controller comprising a storage device adapter, a channel adapter, a cache memory, a control memory, and a plurality of buses connecting therebetween. The channel adapter communicates with a processor and processes input/output requests issued by the processor. The storage device adapter controls a storage device and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means determines a bus mode of bus utilization based on the index.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: June 17, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takao Satoh, Hisaharu Takeuchi, Yasuo Inoue, Akira Yamamoto
  • Patent number: 5613088
    Abstract: A disk array apparatus, which has redundant data arranged in a distributing layout by record includes apparatus for speeding up redundant data updating processing during later updating, apparatus and a read head and write head securely mounted on a single actuator. In operation, old parity data is read out by the read head and then is used to generate new, updated parity data. The updated parity data is written into the record where the old parity data was held within one turn of the disk after the old parity data has been read out.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: March 18, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Kyosuke Achiwa, Akira Yamamoto, Tetsuhiko Fujii, Takao Satoh, Masafumi Nozawa
  • Patent number: 5592630
    Abstract: A data transfer system includes a controller having a cache memory and a transfer information judging unit for reading information stored in a recording medium and for obtaining a first transfer enabled time for storing the information of a track of the recording medium in the cache and a second transfer enabled time for storing the information of the recording medium in the cache memory. A buffer memory temporarily stores the information read from a request track and a pre-load track of the recording medium at every track, in which between the recording medium and the buffer memory and between the buffer memory and the cache there is a ratio of speed for transferring the information from the recording medium to the buffer memory and a speed for transferring the information from the buffer memory to the cache of 1:n (1.ltoreq.n).
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: January 7, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Yamagami, Akira Yamamoto, Takao Satoh
  • Patent number: 5581789
    Abstract: In a highspeed and large-capacity data transfer operation effected between an extended storage unit and an input/output unit, such a data transfer system is provided, capable of preventing a performance deterioration caused by a lack of main storage capacity with employing a buffer having a large memory capacity, and deterioration of a transfer throughput caused by an overhead of an input/output operation due to a use of a buffer having a small memory capacity. There are provided a CCW for directly designating the extended storage unit as an object of a data transfer operation, and a signal line for initiating from a channel the data transfer operation between HSA-extended storage unit. Furthermore, buffers having the planes and with a small memory capacity are prepared on the HSA.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: December 3, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Ueno, Takao Satoh, Tetsuji Ogawa, Toshiyuki Kinoshita, Masaichiro Yoshioka
  • Patent number: 5568628
    Abstract: A storage control unit is connected between a central processing unit having an interface for accessing a first disk unit into which data constructed of a plurality of variable length data records are stored in a first recording format, and a second disk unit into which data constructed of a plurality of fixed length data blocks are recorded in a second recording format. The storage control unit contains a plurality of first-level storage regions having a storage capacity equal to a track of the first disk unit, and the first-level storage regions have a plurality of cache memories constructed of a plurality of second-level storage regions having storage capacities equal to the fixed length blocks in the second recording format.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: October 22, 1996
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.
    Inventors: Takao Satoh, Hiroshi Ichinomiya, Hisaharu Takeuchi, Akira Yamamoto
  • Patent number: 5564116
    Abstract: A storage unit system includes a control apparatus having a unit for reading memory data from a plurality of storage units before increase into a memory of the control apparatus, a preparing unit for preparing parity data newly from the memory data read in the memory, a rearrangement unit for dispersing transfer data from a processor read in the memory and the newly prepared parity data to be written into a plurality of storage units after the increase to perform arrangement of data, a memory unit for storing a write position on the way of the rearrangement of data, a comparison unit for comparing an access position for an access request from the processor with the write position, and a determining unit for determining a data dispersed pattern used in a data access from the processor on the basis of a comparison result of the comparison unit, whereby the storage unit can be increased individually with a unit of one storage unit and dynamically without stop of the system.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: October 8, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Kouji Arai, Takao Satoh, Akira Yamamoto
  • Patent number: 5555389
    Abstract: A storage controller for controlling a storage device storing a plurality of data records and a dump process executed by using this storage device, the storage controller, before a dump process, setting data records to be dumped in a generation fixed status in response to a request from the processor, and when an update request is made on a data record set in a generation fixed status, stores a before-update data record as a generation fixed data record in an unused area of the storage device or in a cache memory or the like before starting an update process, and when receiving a data record read request for the dump process from the processor, examining the presence of a stored generation fixed data record corresponding to the data record specified by the request, and if there is the corresponding generation fixed data record, transferring the data record to the processor in reply to the read request.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: September 10, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takao Satoh, Akira Yamamoto, Shigeo Honma
  • Patent number: 5553307
    Abstract: A disk subsystem provided with a cache has a capability of executing writing of data of discontinuous dirty blocks on a cache memory into a disk and reading of data of discontinuous empty blocks on the cache memory through the effect of just one DMA transfer. When the dirty data discontinuously ranged on a cache segment is written on the disk, the microprocessor provides a bit-map to a harddisk controller (HDC) as control information for data transfer. If an i-th bit of the bit-map is "1", the HDC operates to write the i-th block data sent from a direct memory access controller (DMAC) onto the corresponding sector of the disk. If the i-th bit is "0", the microprocessor serves to stop the write of the data and control a read/write head to wait until it passes the corresponding sector.
    Type: Grant
    Filed: April 16, 1993
    Date of Patent: September 3, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuhiko Fujii, Akira Yamamoto, Tetsuzo Kobashi, Masahiko Sato, Takao Satoh
  • Patent number: 5550975
    Abstract: Block data of logical inconsistency stored in a disk array is inhibited to be transferred to a host computer, by detecting a range where data was written defectively because of a power cut or the like. A processor of a disk array controller allocates a write control table within a non-volatile memory when writing data to a drive group. The write status of each disk drive in each block is supervised by a write status flag. The write statuses include a no write indication status, a writing status, and a write completed status. If all the write statuses of the same block are the write completed status or no write indication status, data is transferred to the host computer. If all the data write statuses of the same block are neither the write completed status nor no write indication status, a read error is informed to the host computer.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: August 27, 1996
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.
    Inventors: Hiroshi Ichinomiya, Takao Satoh, Akira Yamamoto