Patents by Inventor Takao Sonobe

Takao Sonobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6400019
    Abstract: The junction strength between the external terminals and the wiring substrate of a semiconductor device is improved without creating a large size semiconductor device. In the outer periphery of the back surface of an interposer substrate 1Bi on which a semiconductor chip constructing a CSP type semiconductor device 1 is mounted, there are arranged a plurality of bump electrodes 1BB1 whose size in the direction intersecting the sides of the interposer substrate 1B1 is larger than that in the direction along the sides of the interposer substrate 1Bi.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: June 4, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshinori Hirashima, Yasushi Takahashi, Kenji Hanada, Takao Sonobe
  • Patent number: 6335566
    Abstract: Disclosed herein is a semiconductor device in which a main surface of a semiconductor chip is placed over a first main surface of a wiring board so as to be opposed thereto and which includes a plurality of external terminals provided over a second main surface of the wiring board. The plurality of external terminals have a plurality of signal terminals and a plurality of power terminals. The signal terminals are arranged along the periphery of the wiring board and the power terminals are arranged along the inside of a row of the signal terminals. Chip capacitors are placed over the main surface of the semiconductor chip, which lies inside a row of the power terminals. The plurality of signal terminals and power terminals formed over the main surface of the semiconductor chip are connected to a plurality of wires formed over the wiring board respectively. The wiring board is provided with an opening or recess which extends therethrough. The chip capacitors are located within the opening or recess.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: January 1, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Toshinori Hirashima, Takefumi Endo, Kazuo Watanabe, Kenji Hanada, Takao Sonobe