Patents by Inventor Takao Totsuka
Takao Totsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220283745Abstract: A storage system includes a plurality of storage nodes 4 each having one or more storage devices. The storage node includes a CPU. The CPU is configured to select a priority path to be notified as a usable path to a higher-level apparatus among paths which allows access of a predetermined logical unit to which a storage area of the storage device is provided from the higher-level apparatus. The CPU is configured to send the priority path as a reply to an inquiry about a path to the predetermined logical unit from the higher-level apparatus.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Shinri INOUE, Kouji IWAMITSU, Takao TOTSUKA
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Patent number: 11372584Abstract: A storage system includes a plurality of storage nodes 4 each having one or more storage devices. The storage node includes a CPU. The CPU is configured to select a priority path to be notified as a usable path to a higher-level apparatus among paths which allows access of a predetermined logical unit to which a storage area of the storage device is provided from the higher-level apparatus. The CPU is configured to send the priority path as a reply to an inquiry about a path to the predetermined logical unit from the higher-level apparatus.Type: GrantFiled: March 17, 2020Date of Patent: June 28, 2022Assignee: HITACHI, LTD.Inventors: Shinri Inoue, Kouji Iwamitsu, Takao Totsuka
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Publication number: 20210096771Abstract: A storage system includes a plurality of storage nodes 4 each having one or more storage devices. The storage node includes a CPU. The CPU is configured to select a priority path to be notified as a usable path to a higher-level apparatus among paths which allows access of a predetermined logical unit to which a storage area of the storage device is provided from the higher-level apparatus. The CPU is configured to send the priority path as a reply to an inquiry about a path to the predetermined logical unit from the higher-level apparatus.Type: ApplicationFiled: March 17, 2020Publication date: April 1, 2021Inventors: Shinri INOUE, Kouji IWAMITSU, Takao TOTSUKA
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Patent number: 10289564Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.Type: GrantFiled: July 8, 2015Date of Patent: May 14, 2019Assignee: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Takao Totsuka, Toshiomi Moriki, Satoshi Kinugawa
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Patent number: 10042790Abstract: A computer, on which operating systems run, the computer comprising a virtualization function module configured to manage virtual computers. A operating system is configured to run on each of the virtual computers. The virtualization function module includes an interrupt controller. The interrupt controller is configured to hold vector information for managing host-side interrupt vectors, and interrupt vector allocation information for managing allocation of the host-side interrupt vectors to the guest-side interrupt vectors that are set by the operating systems. The virtualization function module is configured to analyze a state of allocation of the host-side interrupt vectors to the guest-side interrupt vectors, and change the allocation of the host-side interrupt vectors to the guest-side interrupt vectors based on a result of the analysis.Type: GrantFiled: March 7, 2014Date of Patent: August 7, 2018Assignee: Hitachi, Ltd.Inventors: Kazuaki Okada, Takao Totsuka
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Publication number: 20180203805Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.Type: ApplicationFiled: July 8, 2015Publication date: July 19, 2018Applicant: HITACHI, LTD.Inventors: Yukari HATTA, Norimitsu HAYAKAWA, Takao TOTSUKA, Toshiomi MORIKI, Satoshi KINUGAWA
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Patent number: 9977740Abstract: A computer, on which a plurality of operating systems run, wherein the plurality of operating systems includes a first operating system and a second operating system configured to generate a plurality of virtual computers. The first operating system runs on a first logical resource, and the second operating system runs on a second logical resource. A third operating system runs on each of the plurality of virtual computers. The third operating system secures a cache memory area in a virtual memory. The second operating system generates location information, which indicates a location of the cache memory area in a physical address space that the second operating system manages. The first operating system obtain data stored in the cache memory area based on the location information.Type: GrantFiled: March 7, 2014Date of Patent: May 22, 2018Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Masatoshi Konagaya, Takao Totsuka, Yukari Hatta
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Publication number: 20170004081Abstract: A computer, on which a plurality of operating systems run, wherein the plurality of operating systems includes a first operating system and a second operating system configured to generate a plurality of virtual computers. The first operating system runs on a first logical resource, and the second operating system runs on a second logical resource. A third operating system runs on each of the plurality of virtual computers. The third operating system secures a cache memory area in a virtual memory. The second operating system generates location information, which indicates a location of the cache memory area in a physical address space that the second operating system manages. The first operating system obtain data stored in the cache memory area based on the location information.Type: ApplicationFiled: March 7, 2014Publication date: January 5, 2017Inventors: Norimitsu HAYAKAWA, Masatoshi KONAGAYA, Takao TOTSUKA, Yukari HATTA
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Publication number: 20160364349Abstract: A computer, on which operating systems run, the computer comprising a virtualization function module configured to manage virtual computers. A operating system is configured to run on each of the virtual computers. The virtualization function module includes an interrupt controller. The interrupt controller is configured to hold vector information for managing host-side interrupt vectors, and interrupt vector allocation information for managing allocation of the host-side interrupt vectors to the guest-side interrupt vectors that are set by the operating systems. The virtualization function module is configured to analyze a state of allocation of the host-side interrupt vectors to the guest-side interrupt vectors, and change the allocation of the host-side interrupt vectors to the guest-side interrupt vectors based on a result of the analysis.Type: ApplicationFiled: March 7, 2014Publication date: December 15, 2016Inventors: Kazuaki OKADA, Takao TOTSUKA
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Patent number: 9323566Abstract: The network connection of a VM (target VM) that has been live-migrated from a first physical computer to a second physical computer is restored in a virtual computer system in which communication is performed using a certain type of information outside the jurisdiction of a virtualization mechanism. When receiving a packet from the VM, the first virtualization mechanism of the first physical computer extracts a certain type of information from the packet and registers the extracted certain type of information in a first management information unit. The first virtualization mechanism transmits the certain type of information in the first management information unit to the second virtualization mechanism of the second physical computer during live migration.Type: GrantFiled: August 22, 2012Date of Patent: April 26, 2016Assignee: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Hiroshi Miki, Shiro Nohara, Takao Totsuka
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Publication number: 20150121372Abstract: The network connection of a VM (target VM) that has been live-migrated from a first physical computer to a second physical computer is restored in a virtual computer system in which communication is performed using a certain type of information outside the jurisdiction of a virtualization mechanism. When receiving a packet from the VM, the first virtualization mechanism of the first physical computer extracts a certain type of information from the packet and registers the extracted certain type of information in a first management information unit. The first virtualization mechanism transmits the certain type of information in the first management information unit to the second virtualization mechanism of the second physical computer during live migration.Type: ApplicationFiled: August 22, 2012Publication date: April 30, 2015Applicant: Hitachi, Ltd.Inventors: Yukari Hatta, Norimitsu Hayakawa, Hiroshi Miki, Shiro Nohara, Takao Totsuka
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Publication number: 20140298340Abstract: Data stored in a memory area of physical memory corresponding to a function read-destination address is accessible in an appropriate manner by a virtual machine. A virtual machine system has a virtual machine management part for managing a virtual machine, and logical processors of virtual machines. The virtual machine management part, on the basis of a physical APCI table, creates a logical APCI table in a logical memory area. A logical processor stores, in an exchange memory area, an address and a size of a memory area in the memory targeted for access by a prescribed function in a control method included in the logical APCI table. The virtual machine management part acquires the address and the size from the exchange memory area, acquires the corresponding memory area data, and stores the acquired data in the logical memory area. The logical processor acquires the data of the logical memory area.Type: ApplicationFiled: October 3, 2012Publication date: October 2, 2014Applicant: HITACHI, LTD.Inventors: Shinya Imaizumi, Takao Totsuka
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Patent number: 8671270Abstract: A computer system including no basic input/output system (BIOS) for operating bootstrap used in initial activation of a legacy operation system is allowed to perform booting of legacy operation system therefor and includes a central processing unit (CPU) and a memory, in which extended firmware and bootstrap program are stored. The extended firmware includes BIOS emulator and a plurality of device drivers. The extended firmware uses the device driver to make the BIOS emulator perform emulation of BIOS operation in response to a BIOS call issued by the bootstrap program.Type: GrantFiled: January 9, 2009Date of Patent: March 11, 2014Assignee: Hitachi, Ltd.Inventors: Harumi Oigawa, Takashi Shimojo, Akira Takeshita, Takao Totsuka
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Patent number: 8479198Abstract: A hypervisor sets all physical areas in an allocation area, which is allocated to a virtual machine from within a physical memory and is configured from a plurality of physical areas, to a write protect mode. In a case where a physical processor identifies that the write-destination area from the virtual machine is in the write protect mode, the hypervisor manages the write-destination area as an updated area, and cancels the write protect mode of the write-destination area. At a certain point in time, the hypervisor copies data inside the updated physical area from within the allocation area to a storage area (a copy area) that differs from the allocation area. In a case where a prescribed failure is detected in the physical area, the hypervisor restores data from the copy area.Type: GrantFiled: February 8, 2011Date of Patent: July 2, 2013Assignee: Hitachi, Ltd.Inventors: Norimitsu Hayakawa, Takao Totsuka
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Publication number: 20110202919Abstract: A hypervisor sets all physical areas in an allocation area, which is allocated to a virtual machine from within a physical memory and is configured from a plurality of physical areas, to a write protect mode. In a case where a physical processor identifies that the write-destination area from the virtual machine is in the write protect mode, the hypervisor manages the write-destination area as an updated area, and cancels the write protect mode of the write-destination area. At a certain point in time, the hypervisor copies data inside the updated physical area from within the allocation area to a storage area (a copy area) that differs from the allocation area. In a case where a prescribed failure is detected in the physical area, the hypervisor restores data from the copy area.Type: ApplicationFiled: February 8, 2011Publication date: August 18, 2011Inventors: NORIMITSU HAYAKAWA, Takao Totsuka
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Patent number: 7760691Abstract: A high-frequency circuit has a duplexer and a filter. The duplexer performs wave separation of send and received signals as input thereto. The filter filters the input send signal. When the send and received signals of the first modulation method are input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer. When the received signal of the first modulation method is input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer, and the send signal of the second modulation method is filtered by the filter.Type: GrantFiled: October 30, 2007Date of Patent: July 20, 2010Assignee: Hitachi Media Electronics Co., Ltd.Inventors: Takao Totsuka, Takashi Shiba, Osamu Hikino
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Patent number: 7570622Abstract: A high-frequency circuit has a duplexer and a filter. The duplexer performs wave separation of send and received signals as input thereto. The filter filters the input send signal. When the send and received signals of the first modulation method are input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer. When the received signal of the first modulation method is input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer, and the send signal of the second modulation method is filtered by the filter.Type: GrantFiled: October 30, 2007Date of Patent: August 4, 2009Assignee: Hitachi Media Electronics Co., Ltd.Inventors: Takao Totsuka, Takashi Shiba, Osamu Hikino
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Publication number: 20090193244Abstract: A computer system including no basic input/output system (BIOS) for operating bootstrap used in initial activation of a legacy operation system is allowed to perform booting of legacy operation system therefor and includes a central processing unit (CPU) and a memory, in which extended firmware and bootstrap program are stored. The extended firmware includes BIOS emulator and a plurality of device drivers. The extended firmware uses the device driver to make the BIOS emulator perform emulation of BIOS operation in response to a BIOS call issued by the bootstrap program.Type: ApplicationFiled: January 9, 2009Publication date: July 30, 2009Inventors: Harumi Oigawa, Takashi Shimojo, Akira Takeshita, Takao Totsuka
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Publication number: 20080137560Abstract: A high-frequency circuit has a duplexer and a filter. The duplexer performs wave separation of send and received signals as input thereto. The filter filters the input send signal. When the send and received signals of the first modulation method are input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer. When the received signal of the first modulation method is input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer, and the send signal of the second modulation method is filtered by the filter.Type: ApplicationFiled: October 30, 2007Publication date: June 12, 2008Applicant: HITACHI MEDIA ELECTRONICS CO., LTD.Inventors: Takao Totsuka, Takashi Shiba, Osamu Hikino
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Publication number: 20080070514Abstract: A high-frequency circuit has a duplexer and a filter. The duplexer performs wave separation of send and received signals as input thereto. The filter filters the input send signal. When the send and received signals of the first modulation method are input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer. When the received signal of the first modulation method is input, the send signal and the received signal of the first modulation method are wave-separated and output by the duplexer, and the send signal of the second modulation method is filtered by the filter.Type: ApplicationFiled: October 30, 2007Publication date: March 20, 2008Applicant: HITACHI MEDIA ELECTRONICS CO., LTD.Inventors: Takao Totsuka, Takashi Shiba, Osamu Hikino