Patents by Inventor Takao Yasue

Takao Yasue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6683589
    Abstract: Barrier ribs of the second type (50) of the same height and material as barrier ribs of the first type (29) are formed on a second substrate in parallel with each other along a first direction (D1) to which display electrodes XE and YE extend. Further, phosphors (28) adhere to both side surface portions (50W3 and 50W4) of the barrier ribs of the second type (50). This achieves a surface discharge type PDP capable of reducing a loss of ultraviolet rays due to repetition of the self absorption and emission of ultraviolet rays, and preventing the leakage of luminescence and discharge to adjacent display lines.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: January 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ko Sano, Kanzou Yoshikawa, Takeo Saikatsu, Takao Yasue, Toyohiro Uchiumi
  • Patent number: 6638129
    Abstract: Barrier ribs of the second type (50) of the same height and material as barrier ribs of the first type (29) are formed on a second substrate in parallel with each other along a first direction (D1) to which display electrodes XE and YE extend. Further, phosphors (28) adhere to both side surface portions (50W3 and 50W4) of the barrier ribs of the second type (50). This achieves a surface discharge type PDP capable of reducing a loss of ultraviolet rays due to repetition of the self absorption and emission of ultraviolet rays, and preventing the leakage of luminescence and discharge to adjacent display lines.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: October 28, 2003
    Assignee: Mitsubishi Denki Kabushiki
    Inventors: Ko Sano, Kanzou Yoshikawa, Takeo Saikatsu, Takao Yasue, Toyohiro Uchiumi
  • Patent number: 6417620
    Abstract: A high performance surface discharge type PDP includes a first glass substrate having a plurality of scanning electrode pairs (X, Y) in parallel with each other and black stripes in parallel with the scanning electrode pairs formed on one main surface thereof and having a dielectric layer covering them. The PDP further includes a second glass substrate including a plurality of address electrodes W formed in parallel with each other in a direction orthogonal to the scanning electrode pairs and having a plurality of barrier ribs in parallel with the address electrodes W for abutting the dielectric layer to form discharge spaces corresponding to each of the address electrodes W. The black stripes formed on the first glass substrate have portions that each intersect with a top of a corresponding one of the plurality of barrier ribs on the second glass substrate which are cut into pieces.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: July 9, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Publication number: 20010026255
    Abstract: Barrier ribs of the second type (50) of the same height and material as barrier ribs of the first type (29) are formed on a second substrate in parallel with each other along a first direction (D1) to which display electrodes XE and YE extend. Further, phosphors (28) adhere to both side surface portions (50W3 and 50W4) of the barrier ribs of the second type (50). This achieves a surface discharge type PDP capable of reducing a loss of ultraviolet rays due to repetition of the self absorption and emission of ultraviolet rays, and preventing the leakage of luminescence and discharge to adjacent display lines.
    Type: Application
    Filed: May 2, 2001
    Publication date: October 4, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Ko Sano, Kanzou Yoshikawa, Takeo Saikatsu, Takao Yasue, Toyohiro Uchiumi
  • Publication number: 20010019318
    Abstract: Barrier ribs of the second type (50) of the same height and material as barrier ribs of the first type (29) are formed on a second substrate in parallel with each other along a first direction (D1) to which display electrodes XE and YE extend. Further, phosphors (28) adhere to both side surface portions (50W3 and 50W4) of the barrier ribs of the second type (50). This achieves a surface discharge type PDP capable of reducing a loss of ultraviolet rays due to repetition of the self absorption and emission of ultraviolet rays, and preventing the leakage of luminescence and discharge to adjacent display lines.
    Type: Application
    Filed: April 9, 2001
    Publication date: September 6, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Ko Sano, Kanzou Yoshikawa, Takeo Saikatsu, Takao Yasue, Toyohiro Uchiumi
  • Patent number: 6249264
    Abstract: Barrier ribs of the second type (50) of the same height and material as barrier ribs of the first type (29) are formed on a second substrate in parallel with each other along a first direction (D1) to which display electrodes XE and YE extend. Further, phosphors (28) adhere to both side surface portions (50W3 and 50W4) of the barrier ribs of the second type (50). This achieves a surface discharge type PDP capable of reducing a loss of ultraviolet rays due to repetition of the self absorption and emission of ultraviolet rays, and preventing the leakage of luminescence and discharge to adjacent display lines.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: June 19, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ko Sano, Kanzou Yoshikawa, Takeo Saikatsu, Takao Yasue, Toyohiro Uchiumi
  • Patent number: 5723982
    Abstract: A method and apparatus for measuring electrical characteristics of a thin surface layer of a sample such as a semiconductor element. A triangular pulse wave of is applied between the sample and a probe needle on a cantilever. By measuring current that flows through the thin surface layer of the sample using the probe needle, I/V characteristics are obtained. A control circuit keep constant the clearance between the probe needle and the thin surface layer of the sample by applying a voltage to a piezoelectric element that supports the sample. I/V characteristics are then measured at a plurality of test points on the thin surface layer of the sample.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: March 3, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takao Yasue, Tadashi Nishioka
  • Patent number: 5652428
    Abstract: A method of use of a scanning probe microscope includes the step of mounting a probe to a scanning probe microscope in ambient atmosphere, the step of drawing on a surface of a standard sample by two-dimensionally scanning while keeping constant a tunnel current under feedback control of a distance between a standard sample and the probe, the step of applying pulse voltage between the probe and the standard sample while two-dimensionally scanning, with feedback control stopped at each scanning point, the step for obtaining drawn image of the surface of the standard sample again, comparing the obtained drawn image with the drawn image obtained in the step of drawing on the surface of the standard sample thereby determining cleanness of the probe, the step of repeating the step of pulse application and the step of determination of cleanness until the probe is cleaned, the step for replacing the standard sample by a sample for measurement after cleanness of the probe is confirmed, and the step of drawing.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: July 29, 1997
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Tadashi Nishioka, Takao Yasue
  • Patent number: 5550372
    Abstract: A device for analyzing foreign matter on semiconductor wafers is provided, which is capable of analyzing a great deal of foreign matter rapidly without requiring the higher level decision capabilities of a skilled analyst. The device for analyzing foreign matter on semiconductor wafers includes a scanning electron microscope (SEM) which obtains the composition ratios of each element of a plurality of foreign matter adhered to semiconductor wafers. A foreign matter plotting section is provided to obtain the distribution of the composition ratios of the plurality of foreign matter on the basis of a result obtained by the SEM. A foreign matter classifying process section classifies the plurality of foreign matter on the basis of the distribution. A foreign matter identifying process section compares the foreign matter classification result with data stored in advance in a foreign matter data base, thereby identifying the foreign matter type.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: August 27, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5530253
    Abstract: A sample stage of a scanning probe microscope head is capable of changing the direction of a sample plane stably over a wide range in a simple operation. Fixtures fix both ends of an outer flexible tube of a flexible shaft. A displacement lead-in portion displaces one end of an inner flexible tube of the flexible shaft relative to the outer flexible tube, and a displacement lead-out portion and a coupling portion transmit the displacement led in the inner flexible tube of the flexible shaft to a sample carrier portion to turn the sample carrier portion about a turn axis, thereby getting a sample plane to change direction.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: June 25, 1996
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Tadashi Nishioka, Takao Yasue
  • Patent number: 5477732
    Abstract: An adhesion measuring apparatus includes a measuring device for measuring a Force-Curve at each of multiple measuring points on a sample surface using a cantilever provided at its distal end with a probe which is made of a material to be formed on the sample surface, and a distribution image forming device for calculating adhesion between a material making up the sample surface and the material to be formed on the sample surface from an output of the measuring device, and forming an image of adhesion distribution on the sample surface.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: December 26, 1995
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takao Yasue, Tadashi Nishioka
  • Patent number: 5469733
    Abstract: A cantilever for an atomic force microscope includes a probe and a cantilever body supporting the probe, the probe deflecting in response to an atomic force between said probe and a sample, at least the surface of the probe including one of a resist film and a sputtered film. One method of manufacturing the cantilever includes selectively etching the surface of a silicon substrate to form an etch pit, forming a resist film in at least the etch pit, forming a nitride film on the resist film, forming a glass base plate on the nitride film in a predetermined area not including the etch pit, and removing the silicon substrate. An atomic force microscope is also provided in which the cantilever is used to measure an atomic force between a sample and the probe having a desired film on a surface.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: November 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Yasue, Tadashi Nishioka
  • Patent number: 5236866
    Abstract: A semiconductor device having multilayer interconnections with reduced formation of hillocks is provided. An Al wiring layer formed on a substrate is patterned for Al wirings. Impurity ions such as Al, Ar, As, P and Sb or the like are implanted on the entire surface including sidewalls of the provided Al wirings. Such impurity ions are implanted to entire surface including sidewalls of the Al wirings, the grain size of granular material at sidewalls of the Al wirings can be made smaller than that of the granular material at inner portions of the metal wirings. As the grain size is reduced, the size of the generated hillocks is reduced. Consequently, short circuits between Al wirings in the same layer can be prevented, enabling provision of highly reliable and highly integrated semiconductor devices.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: August 17, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5193385
    Abstract: A cantilever for an atomic force microscope includes a diamond stylus for opposing a sample for detecting an atomic force, a stylus holding element, at least a portion of which is made of a magnetic material, holding the diamond stylus, and a lever having a secured end and a free end to which the stylus holding element is fastened for being deformed in response to an atomic force acting between the diamond stylus and the sample. A method of manufacturing a cantilever for an atomic force microscope comprises securing a rough diamond stylus to a stylus holding element, at least a portion of the element being magnetic, forming a stylus by grinding the rough diamond, magnetizing the magnetic stylus holding element, applying an adhesive to the surface of a lever, securing the stylus holding element to the lever with the adhesive therebetween with a magnetic field in the vicinity of the lever, removing the magnetic field from the lever after the adhesive has hardened, and demagnetizing the stylus holding element.
    Type: Grant
    Filed: April 16, 1991
    Date of Patent: March 16, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishioka, Takao Yasue, Hiroshi Koyama
  • Patent number: 5147824
    Abstract: A semiconductor wafer having a mark indicating a specified crystal orientation is disclosed. In a preferred embodiment, first and second notches are provided on a circular outer periphery of the semiconductor wafer. A line coupling the vertices of the first and second notches indicates the crystal orientation of the semiconductor wafer. By using such notches as marks for identifying the crystal orientation, the loss of useful area of the semiconductor wafer can be reduced. Generation of slip lines which are crystal defects can be suppressed. Such notches can be formed on the bar member before slicing. By providing the notches on the bar member before individual wafers are cut therefrom, it becomes unnecessary to provide notches on the individual semiconductor wafers one by one.
    Type: Grant
    Filed: August 16, 1991
    Date of Patent: September 15, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5107114
    Abstract: A fine scanning mechanism for an atomic force microscope includes a three-dimensionally displaceable cylindrical piezolectric element, a first probe attaching portion attached to an end of the said cylindrical piezoelectric element, a first probe attached to the first probe attaching portion, a bimorph piezoelectric element attaching portion attached to the end of the cylindrical piezoelectric element, a one-dimensionally displaceable bimorph piezoelectric element attached to the bimorph piezoelectric element attaching portion, a cantilever attaching portion attached to a side of the one-dimensionally displaceable bimorph piezoelectric element, the cantilever having a displacement portion and being attached to the cantilever attaching portion, a second probe attaching portion attached to a side of the displacement portion of the cantilever, a second probe attached to the second probe attaching portion, and a stationary sample tray disposed opposite the second probe.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: April 21, 1992
    Assignee: Mitsubish Denki Kabushiki Kaisha
    Inventors: Tadashi Nishioka, Takao Yasue, Hiroshi Koyama
  • Patent number: 5088290
    Abstract: A transfer vessel apparatus has a device for introducing gas from a liquid nitrogen trap into a vessel body to form and maintain an inert atmosphere in the vessel body. The inert atmosphere maintained in the vessel body enables a sample to be stored for long periods and enables transfer of the sample between different vacuum systems.
    Type: Grant
    Filed: August 22, 1990
    Date of Patent: February 18, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5060043
    Abstract: A semiconductor wafer having a mark indicating a specified crystal orientation is disclosed. In a preferred embodiment, first and second notches are provided on a circular outer periphery of the semiconductor wafer. A line coupling the vertices of the first and second notches indicates the crystal orientation of the semiconductor wafer. By using such notches as marks for identifying the crystal orientation, the loss of useful area of the semiconductor wafer can be reduced. Generation of slip lines which are crystal defects can be suppressed. Such notches can be formed on the bar member before slicing. By providing the notches on the bar member before individual wafers are cut therefrom, it becomes unnecessary to provide notches on the individual semiconductor wafers one by one.
    Type: Grant
    Filed: January 9, 1990
    Date of Patent: October 22, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5043148
    Abstract: A transfer vessel for transporting a specimen between two vacuum apparatuses while maintaining the specimen under a high vacuum. The device has a hermetic container for accommodating a specimen removed from a vacuum apparatus and for supporting the specimen. A pressure reducing device reduces the pressure in the hermetic container by adsorbing a gaseous matter contained therein.
    Type: Grant
    Filed: August 10, 1988
    Date of Patent: August 27, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5040048
    Abstract: A semiconductor device having multilayer interconnections with reduced formation of hillocks is provided. An Al wiring layer formed on a substrate is patterned for Al wirings. Impurity ions such as Al, Ar, As, P and Sb or the like are implanted on the entire surface including sidewalls of the provided Al wirings. Such impurity ions are implanted to entire surface including sidewalls of the Al wirings, the grain size of granular material at sidewalls of the Al wirings can be made smaller than that of the granular material at inner portions of the metal wirings. As the grain size is reduced, the size of the generated hillocks is reduced. Consequently, short circuits between Al wirings in the same layer can be prevented, enabling provision of highly reliable and highly integrated semiconductor devices.
    Type: Grant
    Filed: July 17, 1989
    Date of Patent: August 13, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue