Abstract: Semiconductor devices and method of forming the same include recessing sacrificial layers relative to the channel layers, in a stack of vertically aligned, alternating sacrificial layers and channel layers, to form first recesses. A dual-layer dielectric is deposited that includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the first recesses. The first dielectric material is recessed relative to the second dielectric material to form second recesses. Additional second dielectric material is deposited to fill the second recesses. The second dielectric material and the additional second dielectric material is etched away to create air gaps.

Abstract: Semiconductor devices include a stack of vertically arranged channel layers. A gate stack is formed above, between, and around the vertically arranged channel layers. Source and drain regions and source and drain conductive contacts are formed. Inner spacers are formed between the vertically arranged channel layers, each having an inner air gap and a recessed layer formed from a first dielectric material. Outer spacers are formed between the gate stack and the source and drain conductive contacts, each having a second dielectric material that is pinched off to form an outer air gap.

Abstract: A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.

Abstract: Provided are embodiments of a multi-task learning system with hardware acceleration that includes a resistive random access memory crossbar array. Aspects of the invention includes an input layer that has one or more input layer nodes for performing one or more tasks of the multi-task learning system, a hidden layer that has one or more hidden layer nodes, and a shared hidden layer that has one or more shared hidden layer nodes which represent a parameter, wherein the shared hidden layer nodes are coupled to each of the one or more hidden layer nodes of the hidden layer.

Abstract: An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.

Abstract: In an approach for forming a nonvolatile tunable capacitor device, a first electrode layer is formed distally opposed from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is posited between the first electrode layer and adjacent to the second electrode layer. A phase change material (PCM) layer is posited between the first electrode layer and the second electrode layer adjacent to the dielectric layer. An energizing component is provided to heat the PCM layer to change a phase of the PCM layer. The energizing component may include a heating element or electrical probe in direct contact with the PCM layer, that when energized is configured to apply heat to the PCM layer. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.

Abstract: A circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a stack structure including a first electrode, a metal oxide layer in contact with the first electrode, and a second electrode in contact with the metal oxide layer. A portion of the stack structure is modified by ion implantation, and the modified portion of the stack structure is offset from edges of the stack structure.

Abstract: A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.

Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.

Abstract: A resin composition contains a polyimide resin and an ester-based resin. The ester-based resin is polycarbonate or polyarylate. The polyimide contains a structural unit represented by general formula (1). In general formula (1), X is a divalent organic group shown in group (I), and Y is a divalent group that contains one or more selected from the group consisting of a fluorine group, a trifluoromethyl group, a sulfonic group, a fluorene structure and an alicyclic structure. Each of R1 and R2 is a fluorine atom, an alkyl group having 1 to 20 carbon atoms, or a fluoroalkyl group having 1 to 20 carbon atoms, m is an integer of 1 to 4, and n is an integer of 0 to 4.

Abstract: A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.

Abstract: A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.

Abstract: A semiconductor structure, and a method of making the same, includes an inner spacer located between channel nanosheets on a semiconductor substrate, a first portion of the inner spacer located on a first side of the semiconductor structure and a second portion of the inner spacer located on a second side opposing the first side, the first portion of the inner spacer on the first side including a protruding region extending outwards from a middle top surface of the first portion of the inner spacer, and a metal gate stack in direct contact with the inner spacer, the first portion of the inner spacer including the protruding region pinching off the metal gate stack for increasing a threshold voltage on the first side.

Abstract: A device comprises a non-volatile memory and a control system. The non-volatile memory includes an array of non-volatile memory cells, wherein at least one non-volatile memory cell includes a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes first and second source/drain regions, and a gate structure which comprises a ferroelectric layer, and a gate electrode disposed over the ferroelectric layer. The ferroelectric layer comprises a first region adjacent to the first source/drain region and a second region adjacent to the second source/drain region. The control system is operatively coupled to the non-volatile memory to program the FeFET device to have a logic state among a plurality of different logic states. At least one logic state among the plurality of different logic states corresponds to a polarization state of the FeFET device in which the first and second regions of the ferroelectric layer have respective remnant polarizations with opposite polarities.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: A low voltage forming NVM structure including a plurality of ReRAM devices arranged in a cross bar array and sandwiched between a plurality of first electrically conductive structures and a plurality of second electrically conductive structures. Each first electrically conductive structure is oriented perpendicular to each second electrically conductive structure. The plurality of second electrically conductive structures includes a first set of second electrically conductive structures having a first top trench area A1, and a second set of second electrically conductive structures having a second top trench area A2 that is greater than A1. Each second electrically conductive structure of the first set contacts a surface of at least one of the first electrically conductive structures, and each second electrically conductive structure of the second set contacts a top electrode of at least one of the ReRAM devices.

Abstract: A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

Abstract: A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

Abstract: A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.