Abstract: A laser module includes: a first laser element having a first emission port that emits first laser light; and a second laser element having a second emission port that emits second laser light. The first laser element and the second laser element are disposed such that the first laser light and the second laser light overlap each other.

Abstract: A laser assembly includes a plurality of laser light sources, a plurality of laser light source bases having main surfaces on which the laser light sources are placed and arranged apart from each other, an optical waveguide layer having at least an optical waveguide configured to guide laser light output from the laser light sources, an optical waveguide substrate having a main surface on which the optical waveguide layer is provided, and a plurality of metal films (M) configured to bond the laser light source bases with the optical waveguide substrate. The plurality of metal films (M) correspond to the plurality of laser light source bases and are arranged apart from each other.

Abstract: A light source module includes a chip-on-carrier having a base and a laser diode, a planar lightwave circuit having a substrate and an optical waveguide, and a package having a housing portion configured to house the chip-on-carrier and the planar lightwave circuit. The housing portion has a substructure configured to form a bottom surface, one or more thermal vias penetrating through the substructure, and one or more bumps provided on the substructure. At least one of the bumps is arranged in contact with the planar lightwave circuit and arranged at a position at least partially overlapping the thermal vias when seen from above. The bumps come in contact with the thermal vias or the bumps and the thermal vias are bonded via a metallic pad.

Abstract: What is provided is a subcarrier and a laser module in which, when an optical semiconductor element is formed on the subcarrier, blocking of an irradiation surface of the optical semiconductor element by a structure formed by melting is curbed. This subcarrier is a subcarrier for a laser module including a wafer portion that is constituted of a base and a protective layer formed on a surface of the base, a first metal layer that is formed on the protective layer, a eutectic layer that is formed on the first metal layer, and a second metal layer that is formed on the eutectic layer. The wafer portion has a recessed portion formed in a region overlapping the eutectic layer in a width direction, that is, a region on an outward side of the first metal layer in a longitudinal direction.

Abstract: What is provided is a subcarrier wafer in which chipping, particles, cracking, and the like are curbed. This subcarrier wafer is a subcarrier wafer for a laser module including a wafer, and a plurality of protective layers that are provided on a main surface of the wafer. The plurality of protective layers are arrayed separately, and a part on the main surface of the wafer is exposed.

Abstract: The optical module includes a laser light source part in which a laser light emitting element is formed on one main surface of a first substrate, a mirror part in which an optical scanning mirror element is formed on one main surface of a second substrate, and a lens part in which an optical lens is formed on one main surface of a third substrate, wherein the first substrate and the third substrate are bonded via a metal bonding layer, and the optical module is configured for laser light emitted from the laser light emitting element to be reflected by the optical scanning mirror element via the optical lens.

Abstract: An optical device is provided, the optical device having a laminated substrate in which a plurality of functional layers are laminated, and an optical part and an electronic part disposed on the laminated substrate, wherein one of the functional layers is a first functional layer that the optical part is placed one, and one of other of the functional layers is a second functional layer that is disposed below the first functional layer and the electronic part is placed on, a first wiring is provided on one surface of the first functional layer and a second wiring is provided on one surface of the second functional layer, and a connection terminal of the electronic part is electrically connected to both of the first wiring and the second wiring via a conductive material.

Abstract: A MEMS switch includes a first signal line provided in a first beam, a first GND adjacent to the first signal line, a second signal line provided in a second beam, and a second GND adjacent to the second signal line. A contact terminal is fixed to any one of the first signal line and the second signal line and performs connection between the first signal line and the second signal line according to deformation of the first beam.

Abstract: A MEMS switch includes a first signal line provided in a first beam, a first GND adjacent to the first signal line, a second signal line provided in a second beam, and a second GND adjacent to the second signal line. A contact terminal is fixed to any one of the first signal line and the second signal line and performs connection between the first signal line and the second signal line according to deformation of the first beam.

Abstract: In a piezoelectric element, a piezoelectric film, a first electrode film provided on one surface of the piezoelectric film, and a second electrode film provided on the other surface of the piezoelectric film form a layered structure, an outer contour of the first electrode film and an outer contour of the second electrode film are positioned outside an outer contour of the piezoelectric film as viewed in a layering direction, an organic resin film is in contact with the piezoelectric film, and generation of noise is suppressed.

Abstract: In a piezoelectric element, a piezoelectric film, a first electrode film provided on one surface of the piezoelectric film, and a second electrode film provided on the other surface of the piezoelectric film form a layered structure, an outer contour of the first electrode film and an outer contour of the second electrode film are positioned outside an outer contour of the piezoelectric film as viewed in a layering direction, an organic resin film is in contact with the piezoelectric film, and generation of noise is suppressed.

Abstract: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the SMP virtual connecting unit is provided within the firmware.

Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.

Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.

Abstract: An information processing system may not degrade a processor, if the system is designed so as to satisfy connection restrictions between processors and chipsets. In the system a route switching function is provided to control the connection between a CPU and a BIOS ROM among a plurality of CPUs and the BIOS ROM. When a fault occurs in a particular CPU, a route connecting the BIOS ROM and another CPU in which a fault does not occur is determined, and then the route switching is performed on the basis of the determined route information.

Abstract: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the virtual connecting unit is provided within the firmware.

Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.