Patents by Inventor Takashi Aoyagi
Takashi Aoyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110970Abstract: Main cells that constitute a semiconductor element having a trench gate structure include first cells, and second cells having a structure in which gate insulating films are more easily broken by energization than those in the first cells, and the number of which is smaller than that of the first cells. At a time of driving the semiconductor element, a common gate drive voltage is applied to gate electrodes of the first cells and the second cells. An electrical characteristic is measured to detect failure of the second cells due to energization at the time of driving. The gate electrodes of the failed second cells are electrically isolated from the gate electrodes of the first cells so that the gate drive voltage is not applied to the failed second cells. The failure of the first cells is predicted based on the failure of the second cells.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Applicant: DENSO CORPORATIONInventors: Masataka DEGUCHI, Junya MURAMATSU, Keita KATAOKA, Katsuhiro KUTSUKI, Isao AOYAGI, Takashi TOMINAGA, Ryosuke OKACHI, Takashi KOHYAMA
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Publication number: 20240109286Abstract: A recording device, including a transport roller whose circumference length is different from nozzle array length in a transport direction, performs TP recording control to record a group of test patterns, in which a plurality of test patterns including a first patch and a second patch with different positions in the transport direction are arranged in a main scanning direction, and in which an amount of liquid ejected for a boundary area between the first patch and the second patch is different for each test pattern, wherein, in the TP recording control, records a first TP group and a second TP group at different positions in the transport direction onto a medium, transports the medium by a first distance based on the nozzle array length as a transport between the recording of the first patch and the second patch of the TP, and, as a transport between the recording of the second patch of the first TP group and the recording of the first patch of the second TP group, transports the medium by a second distanceType: ApplicationFiled: September 28, 2023Publication date: April 4, 2024Inventors: Tetsuya MATSUMURA, Shunichi AOYAGI, Takashi KOBAYASHI
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Patent number: 11942623Abstract: Provided are a negative electrode that is for use in a non-aqueous electrolyte secondary battery, includes a porous metal body as a current collector, contains a skeleton-forming agent highly infiltrated in the current collector so that it is less likely to suffer from structural degradation and provides improved cycle durability; and a non-aqueous electrolyte secondary battery including such a negative electrode. The negative electrode for use in a non-aqueous electrolyte secondary battery includes a current collector including a porous metal body; a first negative electrode material disposed in pores of the porous metal body and including a conductive aid, a binder, and a negative electrode active material including a silicon-based material; and a second negative electrode material disposed in pores of the porous metal body and including a skeleton-forming agent including a silicate having a siloxane bond.Type: GrantFiled: January 27, 2022Date of Patent: March 26, 2024Assignee: HONDA MOTOR CO., LTD.Inventors: Kiyoshi Tanaami, Toshimitsu Tanaka, Yuji Isogai, Makiko Takahashi, Shintaro Aoyagi, Takashi Mukai, Yuta Ikeuchi, Taichi Sakamoto, Naoto Yamashita
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Publication number: 20230258998Abstract: An optical device is provided, the optical device having a laminated substrate in which a plurality of functional layers are laminated, and an optical part and an electronic part disposed on the laminated substrate, wherein one of the functional layers is a first functional layer that the optical part is placed one, and one of other of the functional layers is a second functional layer that is disposed below the first functional layer and the electronic part is placed on, a first wiring is provided on one surface of the first functional layer and a second wiring is provided on one surface of the second functional layer, and a connection terminal of the electronic part is electrically connected to both of the first wiring and the second wiring via a conductive material.Type: ApplicationFiled: December 13, 2022Publication date: August 17, 2023Applicant: TDK CORPORATIONInventors: Takashi AOYAGI, Makoto FUKUDA
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Patent number: 10508025Abstract: A MEMS switch includes a first signal line provided in a first beam, a first GND adjacent to the first signal line, a second signal line provided in a second beam, and a second GND adjacent to the second signal line. A contact terminal is fixed to any one of the first signal line and the second signal line and performs connection between the first signal line and the second signal line according to deformation of the first beam.Type: GrantFiled: September 2, 2016Date of Patent: December 17, 2019Assignee: TDK CORPORATIONInventors: Jotaro Akiyama, Kenji Endou, Takashi Aoyagi, Katsunori Osanai, Tohru Inoue
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Publication number: 20190077655Abstract: A MEMS switch includes a first signal line provided in a first beam, a first GND adjacent to the first signal line, a second signal line provided in a second beam, and a second GND adjacent to the second signal line. A contact terminal is fixed to any one of the first signal line and the second signal line and performs connection between the first signal line and the second signal line according to deformation of the first beam.Type: ApplicationFiled: September 2, 2016Publication date: March 14, 2019Applicant: TDK CORPORATIONInventors: Jotaro AKIYAMA, Kenji ENDOU, Takashi AOYAGI, Katsunori OSANAI, Tohru INOUE
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Patent number: 9231182Abstract: In a piezoelectric element, a piezoelectric film, a first electrode film provided on one surface of the piezoelectric film, and a second electrode film provided on the other surface of the piezoelectric film form a layered structure, an outer contour of the first electrode film and an outer contour of the second electrode film are positioned outside an outer contour of the piezoelectric film as viewed in a layering direction, an organic resin film is in contact with the piezoelectric film, and generation of noise is suppressed.Type: GrantFiled: May 21, 2015Date of Patent: January 5, 2016Assignee: TDK CORPORATIONInventors: Hirofumi Natori, Kenichi Tochi, Akihiro Unno, Takashi Aoyagi
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Publication number: 20150340588Abstract: In a piezoelectric element, a piezoelectric film, a first electrode film provided on one surface of the piezoelectric film, and a second electrode film provided on the other surface of the piezoelectric film form a layered structure, an outer contour of the first electrode film and an outer contour of the second electrode film are positioned outside an outer contour of the piezoelectric film as viewed in a layering direction, an organic resin film is in contact with the piezoelectric film, and generation of noise is suppressed.Type: ApplicationFiled: May 21, 2015Publication date: November 26, 2015Inventors: Hirofumi NATORI, Kenichi TOCHI, Akihiro UNNO, Takashi AOYAGI
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Patent number: 8745275Abstract: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the SMP virtual connecting unit is provided within the firmware.Type: GrantFiled: August 15, 2011Date of Patent: June 3, 2014Assignee: Hitachi, Ltd.Inventors: Akio Ikeya, Takashi Aoyagi, Kenji Kashiwagi, Naohiro Sezaki, Kazunori Nakajima
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Patent number: 8683109Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.Type: GrantFiled: January 3, 2013Date of Patent: March 25, 2014Assignee: Hitachi, Ltd.Inventors: Keishi Nakayama, Keitaro Uehara, Takashi Aoyagi, Shinichiro Toya
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Patent number: 8352665Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.Type: GrantFiled: June 18, 2009Date of Patent: January 8, 2013Assignee: Hitachi, Ltd.Inventors: Keishi Nakayama, Keitaro Uehara, Takashi Aoyagi, Shinichiro Toya
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Publication number: 20120159241Abstract: An information processing system may not degrade a processor, if the system is designed so as to satisfy connection restrictions between processors and chipsets. In the system a route switching function is provided to control the connection between a CPU and a BIOS ROM among a plurality of CPUs and the BIOS ROM. When a fault occurs in a particular CPU, a route connecting the BIOS ROM and another CPU in which a fault does not occur is determined, and then the route switching is performed on the basis of the determined route information.Type: ApplicationFiled: December 15, 2011Publication date: June 21, 2012Inventors: MOTOI NISHIJIMA, Takashi Nishiyama, Takashi Aoyagi
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Publication number: 20120054469Abstract: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the virtual connecting unit is provided within the firmware.Type: ApplicationFiled: August 15, 2011Publication date: March 1, 2012Inventors: AKIO IKEYA, Takashi Aoyagi, Kenji Kashiwagi, Naohiro Sezaki, Kazunori Nakajima
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Publication number: 20100036995Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.Type: ApplicationFiled: June 18, 2009Publication date: February 11, 2010Applicant: HITACHI, LTD.Inventors: Keishi Nakayama, Keitaro Uehara, Takashi Aoyagi, Shinichiro Toya
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Patent number: 6815761Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.Type: GrantFiled: April 22, 2003Date of Patent: November 9, 2004Assignee: Renesas Technology CorporationInventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
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Publication number: 20030205731Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.Type: ApplicationFiled: April 22, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
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Patent number: 6583467Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.Type: GrantFiled: June 26, 2002Date of Patent: June 24, 2003Assignee: Hitachi, Ltd.Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
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Patent number: 6573170Abstract: A semiconductor integrated circuit device including a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.Type: GrantFiled: December 27, 2000Date of Patent: June 3, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Aoyagi, Atsushi Ogishima, Hirotaka Kobayashi, Yuji Hara
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Publication number: 20020173091Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.Type: ApplicationFiled: June 26, 2002Publication date: November 21, 2002Applicant: Hitachi, Ltd.Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
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Patent number: D773451Type: GrantFiled: January 16, 2015Date of Patent: December 6, 2016Assignee: Hitachi, Ltd.Inventors: Takashi Aoyagi, Yusuke Mure, Katsuya Sato, Toshihiro Ishiki